base.isa revision 2458 
1////////////////////////////////////////////////////////////////////
2//
3// Base class for sparc instructions, and some support functions
4//
5
6output header {{
7
8        struct condCodes
9        {
10            uint8_t c:1;
11            uint8_t v:1;
12            uint8_t z:1;
13            uint8_t n:1;
14        };
15
16        enum condTest
17        {
18            Always=0x8,
19            Never=0x0,
20            NotEqual=0x9,
21            Equal=0x1,
22            Greater=0xA,
23            LessOrEqual=0x2,
24            GreaterOrEqual=0xB,
25            Less=0x3,
26            GreaterUnsigned=0xC,
27            LessOrEqualUnsigned=0x4,
28            CarryClear=0xD,
29            CarrySet=0x5,
30            Positive=0xE,
31            Negative=0x6,
32            OverflowClear=0xF,
33            OverflowSet=0x7
34        };
35
36        /**
37         * Base class for all SPARC static instructions.
38         */
39        class SparcStaticInst : public StaticInst
40        {
41          protected:
42            // Constructor.
43            SparcStaticInst(const char *mnem,
44                 MachInst _machInst, OpClass __opClass)
45                    : StaticInst(mnem, _machInst, __opClass)
46                {
47                }
48
49            std::string generateDisassembly(Addr pc,
50                const SymbolTable *symtab) const;
51        };
52
53        bool passesCondition(condCodes codes, condTest condition);
54}};
55
56output decoder {{
57
58        std::string SparcStaticInst::generateDisassembly(Addr pc,
59            const SymbolTable *symtab) const
60        {
61            std::stringstream ss;
62
63            ccprintf(ss, "%-10s ", mnemonic);
64
65            // just print the first two source regs... if there's
66            // a third one, it's a read-modify-write dest (Rc),
67            // e.g. for CMOVxx
68            if(_numSrcRegs > 0)
69            {
70                printReg(ss, _srcRegIdx[0]);
71            }
72            if(_numSrcRegs > 1)
73            {
74                ss << ",";
75                printReg(ss, _srcRegIdx[1]);
76            }
77
78            // just print the first dest... if there's a second one,
79            // it's generally implicit
80            if(_numDestRegs > 0)
81            {
82                if(_numSrcRegs > 0)
83                    ss << ",";
84                    printReg(ss, _destRegIdx[0]);
85            }
86
87            return ss.str();
88        }
89
90        bool passesCondition(condCodes codes, condTest condition)
91        {
92            switch(condition)
93            {
94              case Always:
95                return true;
96              case Never:
97                return false;
98              case NotEqual:
99                return !codes.z;
100              case Equal:
101                return codes.z;
102              case Greater:
103                return !(codes.z | (codes.n ^ codes.v));
104              case LessOrEqual:
105                return codes.z | (codes.n ^ codes.v);
106              case GreaterOrEqual:
107                return !(codes.n ^ codes.v);
108              case Less:
109                return (codes.n ^ codes.v);
110              case GreaterUnsigned:
111                return !(codes.c | codes.z);
112              case LessOrEqualUnsigned:
113                return (codes.c | codes.z);
114              case CarryClear:
115                return !codes.c;
116              case CarrySet:
117                return codes.c;
118              case Positive:
119                return !codes.n;
120              case Negative:
121                return codes.n;
122              case OverflowClear:
123                return !codes.v;
124              case OverflowSet:
125                return codes.v;
126            }
127        }
128}};
129
130