isa.hh revision 8747:017e5bbbb4e2 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_HH__
32#define __ARCH_SPARC_ISA_HH__
33
34#include <ostream>
35#include <string>
36
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "config/full_system.hh"
40#include "cpu/cpuevent.hh"
41
42class Checkpoint;
43class EventManager;
44class ThreadContext;
45
46namespace SparcISA
47{
48class ISA
49{
50  private:
51
52    /* ASR Registers */
53    // uint64_t y;          // Y (used in obsolete multiplication)
54    // uint8_t ccr;         // Condition Code Register
55    uint8_t asi;            // Address Space Identifier
56    uint64_t tick;          // Hardware clock-tick counter
57    uint8_t fprs;           // Floating-Point Register State
58    uint64_t gsr;           // General Status Register
59    uint64_t softint;
60    uint64_t tick_cmpr;     // Hardware tick compare registers
61    uint64_t stick;         // Hardware clock-tick counter
62    uint64_t stick_cmpr;    // Hardware tick compare registers
63
64
65    /* Privileged Registers */
66    uint64_t tpc[MaxTL];    // Trap Program Counter (value from
67                            // previous trap level)
68    uint64_t tnpc[MaxTL];   // Trap Next Program Counter (value from
69                            // previous trap level)
70    uint64_t tstate[MaxTL]; // Trap State
71    uint16_t tt[MaxTL];     // Trap Type (Type of trap which occured
72                            // on the previous level)
73    uint64_t tba;           // Trap Base Address
74
75    uint16_t pstate;        // Process State Register
76    uint8_t tl;             // Trap Level
77    uint8_t pil;            // Process Interrupt Register
78    uint8_t cwp;            // Current Window Pointer
79    // uint8_t cansave;     // Savable windows
80    // uint8_t canrestore;  // Restorable windows
81    // uint8_t cleanwin;    // Clean windows
82    // uint8_t otherwin;    // Other windows
83    // uint8_t wstate;      // Window State
84    uint8_t gl;             // Global level register
85
86    /** Hyperprivileged Registers */
87    uint64_t hpstate;       // Hyperprivileged State Register
88    uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
89    uint64_t hintp;
90    uint64_t htba;          // Hyperprivileged Trap Base Address register
91    uint64_t hstick_cmpr;   // Hardware tick compare registers
92
93    uint64_t strandStatusReg;// Per strand status register
94
95    /** Floating point misc registers. */
96    uint64_t fsr;           // Floating-Point State Register
97
98    /** MMU Internal Registers */
99    uint16_t priContext;
100    uint16_t secContext;
101    uint16_t partId;
102    uint64_t lsuCtrlReg;
103
104    uint64_t scratchPad[8];
105
106    uint64_t cpu_mondo_head;
107    uint64_t cpu_mondo_tail;
108    uint64_t dev_mondo_head;
109    uint64_t dev_mondo_tail;
110    uint64_t res_error_head;
111    uint64_t res_error_tail;
112    uint64_t nres_error_head;
113    uint64_t nres_error_tail;
114
115    // These need to check the int_dis field and if 0 then
116    // set appropriate bit in softint and checkinterrutps on the cpu
117    void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
118    MiscReg readFSReg(int miscReg, ThreadContext * tc);
119
120    // Update interrupt state on softint or pil change
121    void checkSoftInt(ThreadContext *tc);
122
123    /** Process a tick compare event and generate an interrupt on the cpu if
124     * appropriate. */
125    void processTickCompare(ThreadContext *tc);
126    void processSTickCompare(ThreadContext *tc);
127    void processHSTickCompare(ThreadContext *tc);
128
129    typedef CpuEventWrapper<ISA,
130            &ISA::processTickCompare> TickCompareEvent;
131    TickCompareEvent *tickCompare;
132
133    typedef CpuEventWrapper<ISA,
134            &ISA::processSTickCompare> STickCompareEvent;
135    STickCompareEvent *sTickCompare;
136
137    typedef CpuEventWrapper<ISA,
138            &ISA::processHSTickCompare> HSTickCompareEvent;
139    HSTickCompareEvent *hSTickCompare;
140
141    static const int NumGlobalRegs = 8;
142    static const int NumWindowedRegs = 24;
143    static const int WindowOverlap = 8;
144
145    static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
146    static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
147    static const int TotalWindowed = NWindows * RegsPerWindow;
148
149    enum InstIntRegOffsets {
150        CurrentGlobalsOffset = 0,
151        CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
152        MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
153        NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
154        NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
155        PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
156        PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
157        TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
158    };
159
160    RegIndex intRegMap[TotalInstIntRegs];
161    void installWindow(int cwp, int offset);
162    void installGlobals(int gl, int offset);
163    void reloadRegMap();
164
165  public:
166
167    void clear();
168
169    void serialize(EventManager *em, std::ostream & os);
170
171    void unserialize(EventManager *em, Checkpoint *cp,
172                     const std::string & section);
173
174  protected:
175
176    bool isHyperPriv() { return (hpstate & (1 << 2)); }
177    bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
178    bool isNonPriv() { return !isPriv(); }
179
180  public:
181
182    MiscReg readMiscRegNoEffect(int miscReg);
183    MiscReg readMiscReg(int miscReg, ThreadContext *tc);
184
185    void setMiscRegNoEffect(int miscReg, const MiscReg val);
186    void setMiscReg(int miscReg, const MiscReg val,
187            ThreadContext *tc);
188
189    int
190    flattenIntIndex(int reg)
191    {
192        assert(reg < TotalInstIntRegs);
193        RegIndex flatIndex = intRegMap[reg];
194        assert(flatIndex < NumIntRegs);
195        return flatIndex;
196    }
197
198    int
199    flattenFloatIndex(int reg)
200    {
201        return reg;
202    }
203
204    ISA()
205    {
206        tickCompare = NULL;
207        sTickCompare = NULL;
208        hSTickCompare = NULL;
209
210        clear();
211    }
212};
213}
214
215#endif
216