isa.hh revision 12479 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_HH__
32#define __ARCH_SPARC_ISA_HH__
33
34#include <ostream>
35#include <string>
36
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "cpu/cpuevent.hh"
40#include "cpu/reg_class.hh"
41#include "sim/sim_object.hh"
42
43class Checkpoint;
44class EventManager;
45struct SparcISAParams;
46class ThreadContext;
47
48namespace SparcISA
49{
50class ISA : public SimObject
51{
52  private:
53
54    /* ASR Registers */
55    // uint64_t y;          // Y (used in obsolete multiplication)
56    // uint8_t ccr;         // Condition Code Register
57    uint8_t asi;            // Address Space Identifier
58    uint64_t tick;          // Hardware clock-tick counter
59    uint8_t fprs;           // Floating-Point Register State
60    uint64_t gsr;           // General Status Register
61    uint64_t softint;
62    uint64_t tick_cmpr;     // Hardware tick compare registers
63    uint64_t stick;         // Hardware clock-tick counter
64    uint64_t stick_cmpr;    // Hardware tick compare registers
65
66
67    /* Privileged Registers */
68    uint64_t tpc[MaxTL];    // Trap Program Counter (value from
69                            // previous trap level)
70    uint64_t tnpc[MaxTL];   // Trap Next Program Counter (value from
71                            // previous trap level)
72    uint64_t tstate[MaxTL]; // Trap State
73    uint16_t tt[MaxTL];     // Trap Type (Type of trap which occured
74                            // on the previous level)
75    uint64_t tba;           // Trap Base Address
76
77    PSTATE pstate;        // Process State Register
78    uint8_t tl;             // Trap Level
79    uint8_t pil;            // Process Interrupt Register
80    uint8_t cwp;            // Current Window Pointer
81    // uint8_t cansave;     // Savable windows
82    // uint8_t canrestore;  // Restorable windows
83    // uint8_t cleanwin;    // Clean windows
84    // uint8_t otherwin;    // Other windows
85    // uint8_t wstate;      // Window State
86    uint8_t gl;             // Global level register
87
88    /** Hyperprivileged Registers */
89    HPSTATE hpstate;       // Hyperprivileged State Register
90    uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
91    uint64_t hintp;
92    uint64_t htba;          // Hyperprivileged Trap Base Address register
93    uint64_t hstick_cmpr;   // Hardware tick compare registers
94
95    uint64_t strandStatusReg;// Per strand status register
96
97    /** Floating point misc registers. */
98    uint64_t fsr;           // Floating-Point State Register
99
100    /** MMU Internal Registers */
101    uint16_t priContext;
102    uint16_t secContext;
103    uint16_t partId;
104    uint64_t lsuCtrlReg;
105
106    uint64_t scratchPad[8];
107
108    uint64_t cpu_mondo_head;
109    uint64_t cpu_mondo_tail;
110    uint64_t dev_mondo_head;
111    uint64_t dev_mondo_tail;
112    uint64_t res_error_head;
113    uint64_t res_error_tail;
114    uint64_t nres_error_head;
115    uint64_t nres_error_tail;
116
117    // These need to check the int_dis field and if 0 then
118    // set appropriate bit in softint and checkinterrutps on the cpu
119    void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
120    MiscReg readFSReg(int miscReg, ThreadContext * tc);
121
122    // Update interrupt state on softint or pil change
123    void checkSoftInt(ThreadContext *tc);
124
125    /** Process a tick compare event and generate an interrupt on the cpu if
126     * appropriate. */
127    void processTickCompare(ThreadContext *tc);
128    void processSTickCompare(ThreadContext *tc);
129    void processHSTickCompare(ThreadContext *tc);
130
131    typedef CpuEventWrapper<ISA,
132            &ISA::processTickCompare> TickCompareEvent;
133    TickCompareEvent *tickCompare;
134
135    typedef CpuEventWrapper<ISA,
136            &ISA::processSTickCompare> STickCompareEvent;
137    STickCompareEvent *sTickCompare;
138
139    typedef CpuEventWrapper<ISA,
140            &ISA::processHSTickCompare> HSTickCompareEvent;
141    HSTickCompareEvent *hSTickCompare;
142
143    static const int NumGlobalRegs = 8;
144    static const int NumWindowedRegs = 24;
145    static const int WindowOverlap = 8;
146
147    static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
148    static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
149    static const int TotalWindowed = NWindows * RegsPerWindow;
150
151    enum InstIntRegOffsets {
152        CurrentGlobalsOffset = 0,
153        CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
154        MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
155        NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
156        NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
157        PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
158        PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
159        TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
160    };
161
162    RegIndex intRegMap[TotalInstIntRegs];
163    void installWindow(int cwp, int offset);
164    void installGlobals(int gl, int offset);
165    void reloadRegMap();
166
167  public:
168
169    void clear();
170
171    void serialize(CheckpointOut &cp) const override;
172    void unserialize(CheckpointIn &cp) override;
173
174    void startup(ThreadContext *tc) {}
175
176    /// Explicitly import the otherwise hidden startup
177    using SimObject::startup;
178
179  protected:
180    bool isHyperPriv() { return hpstate.hpriv; }
181    bool isPriv() { return hpstate.hpriv || pstate.priv; }
182    bool isNonPriv() { return !isPriv(); }
183
184  public:
185
186    MiscReg readMiscRegNoEffect(int miscReg) const;
187    MiscReg readMiscReg(int miscReg, ThreadContext *tc);
188
189    void setMiscRegNoEffect(int miscReg, const MiscReg val);
190    void setMiscReg(int miscReg, const MiscReg val,
191            ThreadContext *tc);
192
193    RegId
194    flattenRegId(const RegId& regId) const
195    {
196        switch (regId.classValue()) {
197          case IntRegClass:
198            return RegId(IntRegClass, flattenIntIndex(regId.index()));
199          case FloatRegClass:
200            return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
201          case CCRegClass:
202            return RegId(CCRegClass, flattenCCIndex(regId.index()));
203          case MiscRegClass:
204            return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
205          default:
206            break;
207        }
208        return regId;
209    }
210
211    int
212    flattenIntIndex(int reg) const
213    {
214        assert(reg < TotalInstIntRegs);
215        RegIndex flatIndex = intRegMap[reg];
216        assert(flatIndex < NumIntRegs);
217        return flatIndex;
218    }
219
220    int
221    flattenFloatIndex(int reg) const
222    {
223        return reg;
224    }
225
226    int
227    flattenVecIndex(int reg) const
228    {
229        return reg;
230    }
231
232    int
233    flattenVecElemIndex(int reg) const
234    {
235        return reg;
236    }
237
238    // dummy
239    int
240    flattenCCIndex(int reg) const
241    {
242        return reg;
243    }
244
245    int
246    flattenMiscIndex(int reg) const
247    {
248        return reg;
249    }
250
251
252    typedef SparcISAParams Params;
253    const Params *params() const;
254
255    ISA(Params *p);
256};
257}
258
259#endif
260