isa.hh revision 6335
110623Smitch.hayenga@arm.com/* 29288Sandreas.hansson@arm.com * Copyright (c) 2009 The Regents of The University of Michigan 39288Sandreas.hansson@arm.com * All rights reserved. 49288Sandreas.hansson@arm.com * 59288Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 69288Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 79288Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 89288Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 99288Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 109288Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 119288Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 129288Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 139288Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 149288Sandreas.hansson@arm.com * this software without specific prior written permission. 159288Sandreas.hansson@arm.com * 169288Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179288Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189288Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199288Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209288Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219288Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229288Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239288Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249288Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259288Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269288Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279288Sandreas.hansson@arm.com * 289288Sandreas.hansson@arm.com * Authors: Gabe Black 299288Sandreas.hansson@arm.com */ 309288Sandreas.hansson@arm.com 319288Sandreas.hansson@arm.com#ifndef __ARCH_SPARC_ISA_HH__ 329288Sandreas.hansson@arm.com#define __ARCH_SPARC_ISA_HH__ 339288Sandreas.hansson@arm.com 349288Sandreas.hansson@arm.com#include "arch/sparc/registers.hh" 359288Sandreas.hansson@arm.com#include "arch/sparc/types.hh" 369288Sandreas.hansson@arm.com#include "config/full_system.hh" 379288Sandreas.hansson@arm.com#include "cpu/cpuevent.hh" 389288Sandreas.hansson@arm.com 399288Sandreas.hansson@arm.com#include <string> 4010623Smitch.hayenga@arm.com#include <ostream> 419288Sandreas.hansson@arm.com 429288Sandreas.hansson@arm.comclass Checkpoint; 4313416Sjavier.bueno@metempsy.comclass EventManager; 448831Smrinmoy.ghosh@arm.comclass ThreadContext; 458832SAli.Saidi@ARM.com 468832SAli.Saidi@ARM.comnamespace SparcISA 4713416Sjavier.bueno@metempsy.com{ 4813416Sjavier.bueno@metempsy.com class ISA 4913416Sjavier.bueno@metempsy.com { 5013416Sjavier.bueno@metempsy.com private: 5113416Sjavier.bueno@metempsy.com 5213416Sjavier.bueno@metempsy.com /* ASR Registers */ 5313416Sjavier.bueno@metempsy.com //uint64_t y; // Y (used in obsolete multiplication) 5413416Sjavier.bueno@metempsy.com //uint8_t ccr; // Condition Code Register 5513416Sjavier.bueno@metempsy.com uint8_t asi; // Address Space Identifier 5613416Sjavier.bueno@metempsy.com uint64_t tick; // Hardware clock-tick counter 5713416Sjavier.bueno@metempsy.com uint8_t fprs; // Floating-Point Register State 5813416Sjavier.bueno@metempsy.com uint64_t gsr; // General Status Register 599288Sandreas.hansson@arm.com uint64_t softint; 608831Smrinmoy.ghosh@arm.com uint64_t tick_cmpr; // Hardware tick compare registers 618831Smrinmoy.ghosh@arm.com uint64_t stick; // Hardware clock-tick counter 629338SAndreas.Sandberg@arm.com uint64_t stick_cmpr; // Hardware tick compare registers 6313416Sjavier.bueno@metempsy.com 6413416Sjavier.bueno@metempsy.com 6513416Sjavier.bueno@metempsy.com /* Privileged Registers */ 6610466Sandreas.hansson@arm.com uint64_t tpc[MaxTL]; // Trap Program Counter (value from 678831Smrinmoy.ghosh@arm.com // previous trap level) 6810623Smitch.hayenga@arm.com uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from 6910623Smitch.hayenga@arm.com // previous trap level) 7010623Smitch.hayenga@arm.com uint64_t tstate[MaxTL]; // Trap State 7110623Smitch.hayenga@arm.com uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured 7210623Smitch.hayenga@arm.com // on the previous level) 7313416Sjavier.bueno@metempsy.com uint64_t tba; // Trap Base Address 7413416Sjavier.bueno@metempsy.com 7513416Sjavier.bueno@metempsy.com uint16_t pstate; // Process State Register 7613416Sjavier.bueno@metempsy.com uint8_t tl; // Trap Level 7713416Sjavier.bueno@metempsy.com uint8_t pil; // Process Interrupt Register 7813416Sjavier.bueno@metempsy.com uint8_t cwp; // Current Window Pointer 7913416Sjavier.bueno@metempsy.com //uint8_t cansave; // Savable windows 8013416Sjavier.bueno@metempsy.com //uint8_t canrestore; // Restorable windows 8113416Sjavier.bueno@metempsy.com //uint8_t cleanwin; // Clean windows 8213416Sjavier.bueno@metempsy.com //uint8_t otherwin; // Other windows 8313416Sjavier.bueno@metempsy.com //uint8_t wstate; // Window State 8413416Sjavier.bueno@metempsy.com uint8_t gl; // Global level register 8513416Sjavier.bueno@metempsy.com 8613416Sjavier.bueno@metempsy.com /** Hyperprivileged Registers */ 8713416Sjavier.bueno@metempsy.com uint64_t hpstate; // Hyperprivileged State Register 8813416Sjavier.bueno@metempsy.com uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register 8913416Sjavier.bueno@metempsy.com uint64_t hintp; 9013416Sjavier.bueno@metempsy.com uint64_t htba; // Hyperprivileged Trap Base Address register 9113416Sjavier.bueno@metempsy.com uint64_t hstick_cmpr; // Hardware tick compare registers 9213416Sjavier.bueno@metempsy.com 9310623Smitch.hayenga@arm.com uint64_t strandStatusReg;// Per strand status register 9410623Smitch.hayenga@arm.com 9510623Smitch.hayenga@arm.com /** Floating point misc registers. */ 9610623Smitch.hayenga@arm.com uint64_t fsr; // Floating-Point State Register 9710623Smitch.hayenga@arm.com 9810623Smitch.hayenga@arm.com /** MMU Internal Registers */ 9910623Smitch.hayenga@arm.com uint16_t priContext; 10010623Smitch.hayenga@arm.com uint16_t secContext; 10110623Smitch.hayenga@arm.com uint16_t partId; 10210623Smitch.hayenga@arm.com uint64_t lsuCtrlReg; 10310623Smitch.hayenga@arm.com 10410623Smitch.hayenga@arm.com uint64_t scratchPad[8]; 10510623Smitch.hayenga@arm.com 10610623Smitch.hayenga@arm.com uint64_t cpu_mondo_head; 10710623Smitch.hayenga@arm.com uint64_t cpu_mondo_tail; 1088831Smrinmoy.ghosh@arm.com uint64_t dev_mondo_head; 1098831Smrinmoy.ghosh@arm.com uint64_t dev_mondo_tail; 1109338SAndreas.Sandberg@arm.com uint64_t res_error_head; 1118831Smrinmoy.ghosh@arm.com uint64_t res_error_tail; 11210623Smitch.hayenga@arm.com uint64_t nres_error_head; 11310623Smitch.hayenga@arm.com uint64_t nres_error_tail; 11410623Smitch.hayenga@arm.com 11510623Smitch.hayenga@arm.com // These need to check the int_dis field and if 0 then 11610623Smitch.hayenga@arm.com // set appropriate bit in softint and checkinterrutps on the cpu 11710623Smitch.hayenga@arm.com#if FULL_SYSTEM 11810623Smitch.hayenga@arm.com void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); 11910623Smitch.hayenga@arm.com MiscReg readFSReg(int miscReg, ThreadContext * tc); 12010623Smitch.hayenga@arm.com 12110623Smitch.hayenga@arm.com // Update interrupt state on softint or pil change 12210623Smitch.hayenga@arm.com void checkSoftInt(ThreadContext *tc); 12310623Smitch.hayenga@arm.com 1248831Smrinmoy.ghosh@arm.com /** Process a tick compare event and generate an interrupt on the cpu if 1258831Smrinmoy.ghosh@arm.com * appropriate. */ 1269338SAndreas.Sandberg@arm.com void processTickCompare(ThreadContext *tc); 1278831Smrinmoy.ghosh@arm.com void processSTickCompare(ThreadContext *tc); 12810623Smitch.hayenga@arm.com void processHSTickCompare(ThreadContext *tc); 129 130 typedef CpuEventWrapper<ISA, 131 &ISA::processTickCompare> TickCompareEvent; 132 TickCompareEvent *tickCompare; 133 134 typedef CpuEventWrapper<ISA, 135 &ISA::processSTickCompare> STickCompareEvent; 136 STickCompareEvent *sTickCompare; 137 138 typedef CpuEventWrapper<ISA, 139 &ISA::processHSTickCompare> HSTickCompareEvent; 140 HSTickCompareEvent *hSTickCompare; 141#endif 142 public: 143 144 void clear(); 145 146 void serialize(EventManager *em, std::ostream & os); 147 148 void unserialize(EventManager *em, Checkpoint *cp, 149 const std::string & section); 150 151 protected: 152 153 bool isHyperPriv() { return (hpstate & (1 << 2)); } 154 bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } 155 bool isNonPriv() { return !isPriv(); } 156 157 public: 158 159 MiscReg readMiscRegNoEffect(int miscReg); 160 MiscReg readMiscReg(int miscReg, ThreadContext *tc); 161 162 void setMiscRegNoEffect(int miscReg, const MiscReg val); 163 void setMiscReg(int miscReg, const MiscReg val, 164 ThreadContext *tc); 165 166 int flattenIntIndex(int reg); 167 168 int 169 flattenFloatIndex(int reg) 170 { 171 return reg; 172 } 173 174 ISA() 175 { 176 clear(); 177 } 178 }; 179} 180 181#endif 182