isa.cc revision 6335
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 316335Sgblack@eecs.umich.edu#include "arch/sparc/asi.hh" 326313Sgblack@eecs.umich.edu#include "arch/sparc/isa.hh" 336335Sgblack@eecs.umich.edu#include "base/bitfield.hh" 346335Sgblack@eecs.umich.edu#include "base/trace.hh" 356335Sgblack@eecs.umich.edu#include "config/full_system.hh" 366335Sgblack@eecs.umich.edu#include "cpu/base.hh" 376313Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 386313Sgblack@eecs.umich.edu 396313Sgblack@eecs.umich.edunamespace SparcISA 406313Sgblack@eecs.umich.edu{ 416313Sgblack@eecs.umich.edu 426335Sgblack@eecs.umich.eduenum RegMask 436335Sgblack@eecs.umich.edu{ 446335Sgblack@eecs.umich.edu PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12) 456335Sgblack@eecs.umich.edu}; 466335Sgblack@eecs.umich.edu 476313Sgblack@eecs.umich.eduvoid 486313Sgblack@eecs.umich.eduISA::clear() 496313Sgblack@eecs.umich.edu{ 506335Sgblack@eecs.umich.edu //y = 0; 516335Sgblack@eecs.umich.edu //ccr = 0; 526335Sgblack@eecs.umich.edu asi = 0; 536335Sgblack@eecs.umich.edu tick = ULL(1) << 63; 546335Sgblack@eecs.umich.edu fprs = 0; 556335Sgblack@eecs.umich.edu gsr = 0; 566335Sgblack@eecs.umich.edu softint = 0; 576335Sgblack@eecs.umich.edu tick_cmpr = 0; 586335Sgblack@eecs.umich.edu stick = 0; 596335Sgblack@eecs.umich.edu stick_cmpr = 0; 606335Sgblack@eecs.umich.edu memset(tpc, 0, sizeof(tpc)); 616335Sgblack@eecs.umich.edu memset(tnpc, 0, sizeof(tnpc)); 626335Sgblack@eecs.umich.edu memset(tstate, 0, sizeof(tstate)); 636335Sgblack@eecs.umich.edu memset(tt, 0, sizeof(tt)); 646335Sgblack@eecs.umich.edu pstate = 0; 656335Sgblack@eecs.umich.edu tl = 0; 666335Sgblack@eecs.umich.edu pil = 0; 676335Sgblack@eecs.umich.edu cwp = 0; 686335Sgblack@eecs.umich.edu //cansave = 0; 696335Sgblack@eecs.umich.edu //canrestore = 0; 706335Sgblack@eecs.umich.edu //cleanwin = 0; 716335Sgblack@eecs.umich.edu //otherwin = 0; 726335Sgblack@eecs.umich.edu //wstate = 0; 736335Sgblack@eecs.umich.edu gl = 0; 746335Sgblack@eecs.umich.edu //In a T1, bit 11 is apparently always 1 756335Sgblack@eecs.umich.edu hpstate = (1 << 11); 766335Sgblack@eecs.umich.edu memset(htstate, 0, sizeof(htstate)); 776335Sgblack@eecs.umich.edu hintp = 0; 786335Sgblack@eecs.umich.edu htba = 0; 796335Sgblack@eecs.umich.edu hstick_cmpr = 0; 806335Sgblack@eecs.umich.edu //This is set this way in Legion for some reason 816335Sgblack@eecs.umich.edu strandStatusReg = 0x50000; 826335Sgblack@eecs.umich.edu fsr = 0; 836335Sgblack@eecs.umich.edu 846335Sgblack@eecs.umich.edu priContext = 0; 856335Sgblack@eecs.umich.edu secContext = 0; 866335Sgblack@eecs.umich.edu partId = 0; 876335Sgblack@eecs.umich.edu lsuCtrlReg = 0; 886335Sgblack@eecs.umich.edu 896335Sgblack@eecs.umich.edu memset(scratchPad, 0, sizeof(scratchPad)); 906335Sgblack@eecs.umich.edu#if FULL_SYSTEM 916335Sgblack@eecs.umich.edu tickCompare = NULL; 926335Sgblack@eecs.umich.edu sTickCompare = NULL; 936335Sgblack@eecs.umich.edu hSTickCompare = NULL; 946335Sgblack@eecs.umich.edu#endif 956313Sgblack@eecs.umich.edu} 966313Sgblack@eecs.umich.edu 976313Sgblack@eecs.umich.eduMiscReg 986313Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int miscReg) 996313Sgblack@eecs.umich.edu{ 1006335Sgblack@eecs.umich.edu 1016335Sgblack@eecs.umich.edu // The three miscRegs are moved up from the switch statement 1026335Sgblack@eecs.umich.edu // due to more frequent calls. 1036335Sgblack@eecs.umich.edu 1046335Sgblack@eecs.umich.edu if (miscReg == MISCREG_GL) 1056335Sgblack@eecs.umich.edu return gl; 1066335Sgblack@eecs.umich.edu if (miscReg == MISCREG_CWP) 1076335Sgblack@eecs.umich.edu return cwp; 1086335Sgblack@eecs.umich.edu if (miscReg == MISCREG_TLB_DATA) { 1096335Sgblack@eecs.umich.edu /* Package up all the data for the tlb: 1106335Sgblack@eecs.umich.edu * 6666555555555544444444443333333333222222222211111111110000000000 1116335Sgblack@eecs.umich.edu * 3210987654321098765432109876543210987654321098765432109876543210 1126335Sgblack@eecs.umich.edu * secContext | priContext | |tl|partid| |||||^hpriv 1136335Sgblack@eecs.umich.edu * ||||^red 1146335Sgblack@eecs.umich.edu * |||^priv 1156335Sgblack@eecs.umich.edu * ||^am 1166335Sgblack@eecs.umich.edu * |^lsuim 1176335Sgblack@eecs.umich.edu * ^lsudm 1186335Sgblack@eecs.umich.edu */ 1196335Sgblack@eecs.umich.edu return bits((uint64_t)hpstate,2,2) | 1206335Sgblack@eecs.umich.edu bits((uint64_t)hpstate,5,5) << 1 | 1216335Sgblack@eecs.umich.edu bits((uint64_t)pstate,3,2) << 2 | 1226335Sgblack@eecs.umich.edu bits((uint64_t)lsuCtrlReg,3,2) << 4 | 1236335Sgblack@eecs.umich.edu bits((uint64_t)partId,7,0) << 8 | 1246335Sgblack@eecs.umich.edu bits((uint64_t)tl,2,0) << 16 | 1256335Sgblack@eecs.umich.edu (uint64_t)priContext << 32 | 1266335Sgblack@eecs.umich.edu (uint64_t)secContext << 48; 1276335Sgblack@eecs.umich.edu } 1286335Sgblack@eecs.umich.edu 1296335Sgblack@eecs.umich.edu switch (miscReg) { 1306335Sgblack@eecs.umich.edu //case MISCREG_TLB_DATA: 1316335Sgblack@eecs.umich.edu // [original contents see above] 1326335Sgblack@eecs.umich.edu //case MISCREG_Y: 1336335Sgblack@eecs.umich.edu // return y; 1346335Sgblack@eecs.umich.edu //case MISCREG_CCR: 1356335Sgblack@eecs.umich.edu // return ccr; 1366335Sgblack@eecs.umich.edu case MISCREG_ASI: 1376335Sgblack@eecs.umich.edu return asi; 1386335Sgblack@eecs.umich.edu case MISCREG_FPRS: 1396335Sgblack@eecs.umich.edu return fprs; 1406335Sgblack@eecs.umich.edu case MISCREG_TICK: 1416335Sgblack@eecs.umich.edu return tick; 1426335Sgblack@eecs.umich.edu case MISCREG_PCR: 1436335Sgblack@eecs.umich.edu panic("PCR not implemented\n"); 1446335Sgblack@eecs.umich.edu case MISCREG_PIC: 1456335Sgblack@eecs.umich.edu panic("PIC not implemented\n"); 1466335Sgblack@eecs.umich.edu case MISCREG_GSR: 1476335Sgblack@eecs.umich.edu return gsr; 1486335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 1496335Sgblack@eecs.umich.edu return softint; 1506335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 1516335Sgblack@eecs.umich.edu return tick_cmpr; 1526335Sgblack@eecs.umich.edu case MISCREG_STICK: 1536335Sgblack@eecs.umich.edu return stick; 1546335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 1556335Sgblack@eecs.umich.edu return stick_cmpr; 1566335Sgblack@eecs.umich.edu 1576335Sgblack@eecs.umich.edu /** Privilged Registers */ 1586335Sgblack@eecs.umich.edu case MISCREG_TPC: 1596335Sgblack@eecs.umich.edu return tpc[tl-1]; 1606335Sgblack@eecs.umich.edu case MISCREG_TNPC: 1616335Sgblack@eecs.umich.edu return tnpc[tl-1]; 1626335Sgblack@eecs.umich.edu case MISCREG_TSTATE: 1636335Sgblack@eecs.umich.edu return tstate[tl-1]; 1646335Sgblack@eecs.umich.edu case MISCREG_TT: 1656335Sgblack@eecs.umich.edu return tt[tl-1]; 1666335Sgblack@eecs.umich.edu case MISCREG_PRIVTICK: 1676335Sgblack@eecs.umich.edu panic("Priviliged access to tick registers not implemented\n"); 1686335Sgblack@eecs.umich.edu case MISCREG_TBA: 1696335Sgblack@eecs.umich.edu return tba; 1706335Sgblack@eecs.umich.edu case MISCREG_PSTATE: 1716335Sgblack@eecs.umich.edu return pstate; 1726335Sgblack@eecs.umich.edu case MISCREG_TL: 1736335Sgblack@eecs.umich.edu return tl; 1746335Sgblack@eecs.umich.edu case MISCREG_PIL: 1756335Sgblack@eecs.umich.edu return pil; 1766335Sgblack@eecs.umich.edu //CWP, GL moved 1776335Sgblack@eecs.umich.edu //case MISCREG_CWP: 1786335Sgblack@eecs.umich.edu // return cwp; 1796335Sgblack@eecs.umich.edu //case MISCREG_CANSAVE: 1806335Sgblack@eecs.umich.edu // return cansave; 1816335Sgblack@eecs.umich.edu //case MISCREG_CANRESTORE: 1826335Sgblack@eecs.umich.edu // return canrestore; 1836335Sgblack@eecs.umich.edu //case MISCREG_CLEANWIN: 1846335Sgblack@eecs.umich.edu // return cleanwin; 1856335Sgblack@eecs.umich.edu //case MISCREG_OTHERWIN: 1866335Sgblack@eecs.umich.edu // return otherwin; 1876335Sgblack@eecs.umich.edu //case MISCREG_WSTATE: 1886335Sgblack@eecs.umich.edu // return wstate; 1896335Sgblack@eecs.umich.edu //case MISCREG_GL: 1906335Sgblack@eecs.umich.edu // return gl; 1916335Sgblack@eecs.umich.edu 1926335Sgblack@eecs.umich.edu /** Hyper privileged registers */ 1936335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 1946335Sgblack@eecs.umich.edu return hpstate; 1956335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 1966335Sgblack@eecs.umich.edu return htstate[tl-1]; 1976335Sgblack@eecs.umich.edu case MISCREG_HINTP: 1986335Sgblack@eecs.umich.edu return hintp; 1996335Sgblack@eecs.umich.edu case MISCREG_HTBA: 2006335Sgblack@eecs.umich.edu return htba; 2016335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2026335Sgblack@eecs.umich.edu return strandStatusReg; 2036335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2046335Sgblack@eecs.umich.edu return hstick_cmpr; 2056335Sgblack@eecs.umich.edu 2066335Sgblack@eecs.umich.edu /** Floating Point Status Register */ 2076335Sgblack@eecs.umich.edu case MISCREG_FSR: 2086335Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr); 2096335Sgblack@eecs.umich.edu return fsr; 2106335Sgblack@eecs.umich.edu 2116335Sgblack@eecs.umich.edu case MISCREG_MMU_P_CONTEXT: 2126335Sgblack@eecs.umich.edu return priContext; 2136335Sgblack@eecs.umich.edu case MISCREG_MMU_S_CONTEXT: 2146335Sgblack@eecs.umich.edu return secContext; 2156335Sgblack@eecs.umich.edu case MISCREG_MMU_PART_ID: 2166335Sgblack@eecs.umich.edu return partId; 2176335Sgblack@eecs.umich.edu case MISCREG_MMU_LSU_CTRL: 2186335Sgblack@eecs.umich.edu return lsuCtrlReg; 2196335Sgblack@eecs.umich.edu 2206335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R0: 2216335Sgblack@eecs.umich.edu return scratchPad[0]; 2226335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R1: 2236335Sgblack@eecs.umich.edu return scratchPad[1]; 2246335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R2: 2256335Sgblack@eecs.umich.edu return scratchPad[2]; 2266335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R3: 2276335Sgblack@eecs.umich.edu return scratchPad[3]; 2286335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R4: 2296335Sgblack@eecs.umich.edu return scratchPad[4]; 2306335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R5: 2316335Sgblack@eecs.umich.edu return scratchPad[5]; 2326335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R6: 2336335Sgblack@eecs.umich.edu return scratchPad[6]; 2346335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R7: 2356335Sgblack@eecs.umich.edu return scratchPad[7]; 2366335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2376335Sgblack@eecs.umich.edu return cpu_mondo_head; 2386335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 2396335Sgblack@eecs.umich.edu return cpu_mondo_tail; 2406335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 2416335Sgblack@eecs.umich.edu return dev_mondo_head; 2426335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 2436335Sgblack@eecs.umich.edu return dev_mondo_tail; 2446335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 2456335Sgblack@eecs.umich.edu return res_error_head; 2466335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 2476335Sgblack@eecs.umich.edu return res_error_tail; 2486335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 2496335Sgblack@eecs.umich.edu return nres_error_head; 2506335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 2516335Sgblack@eecs.umich.edu return nres_error_tail; 2526335Sgblack@eecs.umich.edu default: 2536335Sgblack@eecs.umich.edu panic("Miscellaneous register %d not implemented\n", miscReg); 2546335Sgblack@eecs.umich.edu } 2556313Sgblack@eecs.umich.edu} 2566313Sgblack@eecs.umich.edu 2576313Sgblack@eecs.umich.eduMiscReg 2586335Sgblack@eecs.umich.eduISA::readMiscReg(int miscReg, ThreadContext * tc) 2596313Sgblack@eecs.umich.edu{ 2606335Sgblack@eecs.umich.edu switch (miscReg) { 2616335Sgblack@eecs.umich.edu // tick and stick are aliased to each other in niagra 2626335Sgblack@eecs.umich.edu // well store the tick data in stick and the interrupt bit in tick 2636335Sgblack@eecs.umich.edu case MISCREG_STICK: 2646335Sgblack@eecs.umich.edu case MISCREG_TICK: 2656335Sgblack@eecs.umich.edu case MISCREG_PRIVTICK: 2666335Sgblack@eecs.umich.edu // I'm not sure why legion ignores the lowest two bits, but we'll go 2676335Sgblack@eecs.umich.edu // with it 2686335Sgblack@eecs.umich.edu // change from curCycle() to instCount() until we're done with legion 2696335Sgblack@eecs.umich.edu DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n", 2706335Sgblack@eecs.umich.edu tc->getCpuPtr()->instCount(), stick); 2716335Sgblack@eecs.umich.edu return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) | 2726335Sgblack@eecs.umich.edu mbits(tick,63,63); 2736335Sgblack@eecs.umich.edu case MISCREG_FPRS: 2746335Sgblack@eecs.umich.edu // in legion if fp is enabled du and dl are set 2756335Sgblack@eecs.umich.edu return fprs | 0x3; 2766335Sgblack@eecs.umich.edu case MISCREG_PCR: 2776335Sgblack@eecs.umich.edu case MISCREG_PIC: 2786335Sgblack@eecs.umich.edu panic("Performance Instrumentation not impl\n"); 2796335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_CLR: 2806335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_SET: 2816335Sgblack@eecs.umich.edu panic("Can read from softint clr/set\n"); 2826335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 2836335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 2846335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 2856335Sgblack@eecs.umich.edu case MISCREG_HINTP: 2866335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 2876335Sgblack@eecs.umich.edu case MISCREG_HTBA: 2886335Sgblack@eecs.umich.edu case MISCREG_HVER: 2896335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2906335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2916335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2926335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 2936335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 2946335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 2956335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 2966335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 2976335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 2986335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 2996335Sgblack@eecs.umich.edu#if FULL_SYSTEM 3006335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 3016335Sgblack@eecs.umich.edu return readFSReg(miscReg, tc); 3026335Sgblack@eecs.umich.edu#else 3036335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 3046335Sgblack@eecs.umich.edu //HPSTATE is special because because sometimes in privilege 3056335Sgblack@eecs.umich.edu //checks for instructions it will read HPSTATE to make sure 3066335Sgblack@eecs.umich.edu //the priv. level is ok So, we'll just have to tell it it 3076335Sgblack@eecs.umich.edu //isn't, instead of panicing. 3086335Sgblack@eecs.umich.edu return 0; 3096335Sgblack@eecs.umich.edu 3106335Sgblack@eecs.umich.edu panic("Accessing Fullsystem register %d in SE mode\n", miscReg); 3116335Sgblack@eecs.umich.edu#endif 3126335Sgblack@eecs.umich.edu 3136335Sgblack@eecs.umich.edu } 3146335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg); 3156313Sgblack@eecs.umich.edu} 3166313Sgblack@eecs.umich.edu 3176313Sgblack@eecs.umich.eduvoid 3186335Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int miscReg, MiscReg val) 3196313Sgblack@eecs.umich.edu{ 3206335Sgblack@eecs.umich.edu switch (miscReg) { 3216335Sgblack@eecs.umich.edu// case MISCREG_Y: 3226335Sgblack@eecs.umich.edu// y = val; 3236335Sgblack@eecs.umich.edu// break; 3246335Sgblack@eecs.umich.edu// case MISCREG_CCR: 3256335Sgblack@eecs.umich.edu// ccr = val; 3266335Sgblack@eecs.umich.edu// break; 3276335Sgblack@eecs.umich.edu case MISCREG_ASI: 3286335Sgblack@eecs.umich.edu asi = val; 3296335Sgblack@eecs.umich.edu break; 3306335Sgblack@eecs.umich.edu case MISCREG_FPRS: 3316335Sgblack@eecs.umich.edu fprs = val; 3326335Sgblack@eecs.umich.edu break; 3336335Sgblack@eecs.umich.edu case MISCREG_TICK: 3346335Sgblack@eecs.umich.edu tick = val; 3356335Sgblack@eecs.umich.edu break; 3366335Sgblack@eecs.umich.edu case MISCREG_PCR: 3376335Sgblack@eecs.umich.edu panic("PCR not implemented\n"); 3386335Sgblack@eecs.umich.edu case MISCREG_PIC: 3396335Sgblack@eecs.umich.edu panic("PIC not implemented\n"); 3406335Sgblack@eecs.umich.edu case MISCREG_GSR: 3416335Sgblack@eecs.umich.edu gsr = val; 3426335Sgblack@eecs.umich.edu break; 3436335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 3446335Sgblack@eecs.umich.edu softint = val; 3456335Sgblack@eecs.umich.edu break; 3466335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 3476335Sgblack@eecs.umich.edu tick_cmpr = val; 3486335Sgblack@eecs.umich.edu break; 3496335Sgblack@eecs.umich.edu case MISCREG_STICK: 3506335Sgblack@eecs.umich.edu stick = val; 3516335Sgblack@eecs.umich.edu break; 3526335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 3536335Sgblack@eecs.umich.edu stick_cmpr = val; 3546335Sgblack@eecs.umich.edu break; 3556335Sgblack@eecs.umich.edu 3566335Sgblack@eecs.umich.edu /** Privilged Registers */ 3576335Sgblack@eecs.umich.edu case MISCREG_TPC: 3586335Sgblack@eecs.umich.edu tpc[tl-1] = val; 3596335Sgblack@eecs.umich.edu break; 3606335Sgblack@eecs.umich.edu case MISCREG_TNPC: 3616335Sgblack@eecs.umich.edu tnpc[tl-1] = val; 3626335Sgblack@eecs.umich.edu break; 3636335Sgblack@eecs.umich.edu case MISCREG_TSTATE: 3646335Sgblack@eecs.umich.edu tstate[tl-1] = val; 3656335Sgblack@eecs.umich.edu break; 3666335Sgblack@eecs.umich.edu case MISCREG_TT: 3676335Sgblack@eecs.umich.edu tt[tl-1] = val; 3686335Sgblack@eecs.umich.edu break; 3696335Sgblack@eecs.umich.edu case MISCREG_PRIVTICK: 3706335Sgblack@eecs.umich.edu panic("Priviliged access to tick regesiters not implemented\n"); 3716335Sgblack@eecs.umich.edu case MISCREG_TBA: 3726335Sgblack@eecs.umich.edu // clear lower 7 bits on writes. 3736335Sgblack@eecs.umich.edu tba = val & ULL(~0x7FFF); 3746335Sgblack@eecs.umich.edu break; 3756335Sgblack@eecs.umich.edu case MISCREG_PSTATE: 3766335Sgblack@eecs.umich.edu pstate = (val & PSTATE_MASK); 3776335Sgblack@eecs.umich.edu break; 3786335Sgblack@eecs.umich.edu case MISCREG_TL: 3796335Sgblack@eecs.umich.edu tl = val; 3806335Sgblack@eecs.umich.edu break; 3816335Sgblack@eecs.umich.edu case MISCREG_PIL: 3826335Sgblack@eecs.umich.edu pil = val; 3836335Sgblack@eecs.umich.edu break; 3846335Sgblack@eecs.umich.edu case MISCREG_CWP: 3856335Sgblack@eecs.umich.edu cwp = val; 3866335Sgblack@eecs.umich.edu break; 3876335Sgblack@eecs.umich.edu// case MISCREG_CANSAVE: 3886335Sgblack@eecs.umich.edu// cansave = val; 3896335Sgblack@eecs.umich.edu// break; 3906335Sgblack@eecs.umich.edu// case MISCREG_CANRESTORE: 3916335Sgblack@eecs.umich.edu// canrestore = val; 3926335Sgblack@eecs.umich.edu// break; 3936335Sgblack@eecs.umich.edu// case MISCREG_CLEANWIN: 3946335Sgblack@eecs.umich.edu// cleanwin = val; 3956335Sgblack@eecs.umich.edu// break; 3966335Sgblack@eecs.umich.edu// case MISCREG_OTHERWIN: 3976335Sgblack@eecs.umich.edu// otherwin = val; 3986335Sgblack@eecs.umich.edu// break; 3996335Sgblack@eecs.umich.edu// case MISCREG_WSTATE: 4006335Sgblack@eecs.umich.edu// wstate = val; 4016335Sgblack@eecs.umich.edu// break; 4026335Sgblack@eecs.umich.edu case MISCREG_GL: 4036335Sgblack@eecs.umich.edu gl = val; 4046335Sgblack@eecs.umich.edu break; 4056335Sgblack@eecs.umich.edu 4066335Sgblack@eecs.umich.edu /** Hyper privileged registers */ 4076335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 4086335Sgblack@eecs.umich.edu hpstate = val; 4096335Sgblack@eecs.umich.edu break; 4106335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 4116335Sgblack@eecs.umich.edu htstate[tl-1] = val; 4126335Sgblack@eecs.umich.edu break; 4136335Sgblack@eecs.umich.edu case MISCREG_HINTP: 4146335Sgblack@eecs.umich.edu hintp = val; 4156335Sgblack@eecs.umich.edu case MISCREG_HTBA: 4166335Sgblack@eecs.umich.edu htba = val; 4176335Sgblack@eecs.umich.edu break; 4186335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 4196335Sgblack@eecs.umich.edu strandStatusReg = val; 4206335Sgblack@eecs.umich.edu break; 4216335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 4226335Sgblack@eecs.umich.edu hstick_cmpr = val; 4236335Sgblack@eecs.umich.edu break; 4246335Sgblack@eecs.umich.edu 4256335Sgblack@eecs.umich.edu /** Floating Point Status Register */ 4266335Sgblack@eecs.umich.edu case MISCREG_FSR: 4276335Sgblack@eecs.umich.edu fsr = val; 4286335Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr); 4296335Sgblack@eecs.umich.edu break; 4306335Sgblack@eecs.umich.edu 4316335Sgblack@eecs.umich.edu case MISCREG_MMU_P_CONTEXT: 4326335Sgblack@eecs.umich.edu priContext = val; 4336335Sgblack@eecs.umich.edu break; 4346335Sgblack@eecs.umich.edu case MISCREG_MMU_S_CONTEXT: 4356335Sgblack@eecs.umich.edu secContext = val; 4366335Sgblack@eecs.umich.edu break; 4376335Sgblack@eecs.umich.edu case MISCREG_MMU_PART_ID: 4386335Sgblack@eecs.umich.edu partId = val; 4396335Sgblack@eecs.umich.edu break; 4406335Sgblack@eecs.umich.edu case MISCREG_MMU_LSU_CTRL: 4416335Sgblack@eecs.umich.edu lsuCtrlReg = val; 4426335Sgblack@eecs.umich.edu break; 4436335Sgblack@eecs.umich.edu 4446335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R0: 4456335Sgblack@eecs.umich.edu scratchPad[0] = val; 4466335Sgblack@eecs.umich.edu break; 4476335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R1: 4486335Sgblack@eecs.umich.edu scratchPad[1] = val; 4496335Sgblack@eecs.umich.edu break; 4506335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R2: 4516335Sgblack@eecs.umich.edu scratchPad[2] = val; 4526335Sgblack@eecs.umich.edu break; 4536335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R3: 4546335Sgblack@eecs.umich.edu scratchPad[3] = val; 4556335Sgblack@eecs.umich.edu break; 4566335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R4: 4576335Sgblack@eecs.umich.edu scratchPad[4] = val; 4586335Sgblack@eecs.umich.edu break; 4596335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R5: 4606335Sgblack@eecs.umich.edu scratchPad[5] = val; 4616335Sgblack@eecs.umich.edu break; 4626335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R6: 4636335Sgblack@eecs.umich.edu scratchPad[6] = val; 4646335Sgblack@eecs.umich.edu break; 4656335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R7: 4666335Sgblack@eecs.umich.edu scratchPad[7] = val; 4676335Sgblack@eecs.umich.edu break; 4686335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 4696335Sgblack@eecs.umich.edu cpu_mondo_head = val; 4706335Sgblack@eecs.umich.edu break; 4716335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 4726335Sgblack@eecs.umich.edu cpu_mondo_tail = val; 4736335Sgblack@eecs.umich.edu break; 4746335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 4756335Sgblack@eecs.umich.edu dev_mondo_head = val; 4766335Sgblack@eecs.umich.edu break; 4776335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 4786335Sgblack@eecs.umich.edu dev_mondo_tail = val; 4796335Sgblack@eecs.umich.edu break; 4806335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 4816335Sgblack@eecs.umich.edu res_error_head = val; 4826335Sgblack@eecs.umich.edu break; 4836335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 4846335Sgblack@eecs.umich.edu res_error_tail = val; 4856335Sgblack@eecs.umich.edu break; 4866335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 4876335Sgblack@eecs.umich.edu nres_error_head = val; 4886335Sgblack@eecs.umich.edu break; 4896335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 4906335Sgblack@eecs.umich.edu nres_error_tail = val; 4916335Sgblack@eecs.umich.edu break; 4926335Sgblack@eecs.umich.edu default: 4936335Sgblack@eecs.umich.edu panic("Miscellaneous register %d not implemented\n", miscReg); 4946335Sgblack@eecs.umich.edu } 4956313Sgblack@eecs.umich.edu} 4966313Sgblack@eecs.umich.edu 4976313Sgblack@eecs.umich.eduvoid 4986335Sgblack@eecs.umich.eduISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 4996313Sgblack@eecs.umich.edu{ 5006335Sgblack@eecs.umich.edu MiscReg new_val = val; 5016335Sgblack@eecs.umich.edu 5026335Sgblack@eecs.umich.edu switch (miscReg) { 5036335Sgblack@eecs.umich.edu case MISCREG_STICK: 5046335Sgblack@eecs.umich.edu case MISCREG_TICK: 5056335Sgblack@eecs.umich.edu // stick and tick are same thing on niagra 5066335Sgblack@eecs.umich.edu // use stick for offset and tick for holding intrrupt bit 5076335Sgblack@eecs.umich.edu stick = mbits(val,62,0) - tc->getCpuPtr()->instCount(); 5086335Sgblack@eecs.umich.edu tick = mbits(val,63,63); 5096335Sgblack@eecs.umich.edu DPRINTF(Timer, "Writing TICK=%#X\n", val); 5106335Sgblack@eecs.umich.edu break; 5116335Sgblack@eecs.umich.edu case MISCREG_FPRS: 5126335Sgblack@eecs.umich.edu //Configure the fpu based on the fprs 5136335Sgblack@eecs.umich.edu break; 5146335Sgblack@eecs.umich.edu case MISCREG_PCR: 5156335Sgblack@eecs.umich.edu //Set up performance counting based on pcr value 5166335Sgblack@eecs.umich.edu break; 5176335Sgblack@eecs.umich.edu case MISCREG_PSTATE: 5186335Sgblack@eecs.umich.edu pstate = val & PSTATE_MASK; 5196335Sgblack@eecs.umich.edu return; 5206335Sgblack@eecs.umich.edu case MISCREG_TL: 5216335Sgblack@eecs.umich.edu tl = val; 5226335Sgblack@eecs.umich.edu#if FULL_SYSTEM 5236335Sgblack@eecs.umich.edu if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) 5246335Sgblack@eecs.umich.edu tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 5256335Sgblack@eecs.umich.edu else 5266335Sgblack@eecs.umich.edu tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 5276335Sgblack@eecs.umich.edu#endif 5286335Sgblack@eecs.umich.edu return; 5296335Sgblack@eecs.umich.edu case MISCREG_CWP: 5306335Sgblack@eecs.umich.edu new_val = val >= NWindows ? NWindows - 1 : val; 5316335Sgblack@eecs.umich.edu if (val >= NWindows) 5326335Sgblack@eecs.umich.edu new_val = NWindows - 1; 5336335Sgblack@eecs.umich.edu break; 5346335Sgblack@eecs.umich.edu case MISCREG_GL: 5356335Sgblack@eecs.umich.edu break; 5366335Sgblack@eecs.umich.edu case MISCREG_PIL: 5376335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 5386335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_SET: 5396335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_CLR: 5406335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 5416335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 5426335Sgblack@eecs.umich.edu case MISCREG_HINTP: 5436335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 5446335Sgblack@eecs.umich.edu case MISCREG_HTBA: 5456335Sgblack@eecs.umich.edu case MISCREG_HVER: 5466335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 5476335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 5486335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 5496335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 5506335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 5516335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 5526335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 5536335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 5546335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 5556335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 5566335Sgblack@eecs.umich.edu#if FULL_SYSTEM 5576335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 5586335Sgblack@eecs.umich.edu setFSReg(miscReg, val, tc); 5596335Sgblack@eecs.umich.edu return; 5606335Sgblack@eecs.umich.edu#else 5616335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 5626335Sgblack@eecs.umich.edu //HPSTATE is special because normal trap processing saves HPSTATE when 5636335Sgblack@eecs.umich.edu //it goes into a trap, and restores it when it returns. 5646335Sgblack@eecs.umich.edu return; 5656335Sgblack@eecs.umich.edu panic("Accessing Fullsystem register %d to %#x in SE mode\n", 5666335Sgblack@eecs.umich.edu miscReg, val); 5676335Sgblack@eecs.umich.edu#endif 5686335Sgblack@eecs.umich.edu } 5696335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, new_val); 5706335Sgblack@eecs.umich.edu} 5716335Sgblack@eecs.umich.edu 5726335Sgblack@eecs.umich.eduvoid 5736335Sgblack@eecs.umich.eduISA::serialize(EventManager *em, std::ostream &os) 5746335Sgblack@eecs.umich.edu{ 5756335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(asi); 5766335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick); 5776335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(fprs); 5786335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(gsr); 5796335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(softint); 5806335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick_cmpr); 5816335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(stick); 5826335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(stick_cmpr); 5836335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tpc,MaxTL); 5846335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tnpc,MaxTL); 5856335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tstate,MaxTL); 5866335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tt,MaxTL); 5876335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tba); 5886335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(pstate); 5896335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tl); 5906335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(pil); 5916335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cwp); 5926335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(gl); 5936335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hpstate); 5946335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(htstate,MaxTL); 5956335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hintp); 5966335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(htba); 5976335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hstick_cmpr); 5986335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(strandStatusReg); 5996335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(fsr); 6006335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(priContext); 6016335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(secContext); 6026335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(partId); 6036335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(lsuCtrlReg); 6046335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(scratchPad,8); 6056335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cpu_mondo_head); 6066335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cpu_mondo_tail); 6076335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(dev_mondo_head); 6086335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(dev_mondo_tail); 6096335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(res_error_head); 6106335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(res_error_tail); 6116335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nres_error_head); 6126335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nres_error_tail); 6136335Sgblack@eecs.umich.edu#if FULL_SYSTEM 6146335Sgblack@eecs.umich.edu Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; 6156335Sgblack@eecs.umich.edu ThreadContext *tc = NULL; 6166335Sgblack@eecs.umich.edu BaseCPU *cpu = NULL; 6176335Sgblack@eecs.umich.edu int tc_num = 0; 6186335Sgblack@eecs.umich.edu bool tick_intr_sched = true; 6196335Sgblack@eecs.umich.edu 6206335Sgblack@eecs.umich.edu if (tickCompare) 6216335Sgblack@eecs.umich.edu tc = tickCompare->getTC(); 6226335Sgblack@eecs.umich.edu else if (sTickCompare) 6236335Sgblack@eecs.umich.edu tc = sTickCompare->getTC(); 6246335Sgblack@eecs.umich.edu else if (hSTickCompare) 6256335Sgblack@eecs.umich.edu tc = hSTickCompare->getTC(); 6266335Sgblack@eecs.umich.edu else 6276335Sgblack@eecs.umich.edu tick_intr_sched = false; 6286335Sgblack@eecs.umich.edu 6296335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick_intr_sched); 6306335Sgblack@eecs.umich.edu 6316335Sgblack@eecs.umich.edu if (tc) { 6326335Sgblack@eecs.umich.edu cpu = tc->getCpuPtr(); 6336335Sgblack@eecs.umich.edu tc_num = cpu->findContext(tc); 6346335Sgblack@eecs.umich.edu if (tickCompare && tickCompare->scheduled()) 6356335Sgblack@eecs.umich.edu tick_cmp = tickCompare->when(); 6366335Sgblack@eecs.umich.edu if (sTickCompare && sTickCompare->scheduled()) 6376335Sgblack@eecs.umich.edu stick_cmp = sTickCompare->when(); 6386335Sgblack@eecs.umich.edu if (hSTickCompare && hSTickCompare->scheduled()) 6396335Sgblack@eecs.umich.edu hstick_cmp = hSTickCompare->when(); 6406335Sgblack@eecs.umich.edu 6416335Sgblack@eecs.umich.edu SERIALIZE_OBJPTR(cpu); 6426335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tc_num); 6436335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick_cmp); 6446335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(stick_cmp); 6456335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hstick_cmp); 6466335Sgblack@eecs.umich.edu } 6476335Sgblack@eecs.umich.edu#endif 6486335Sgblack@eecs.umich.edu} 6496335Sgblack@eecs.umich.edu 6506335Sgblack@eecs.umich.eduvoid 6516335Sgblack@eecs.umich.eduISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) 6526335Sgblack@eecs.umich.edu{ 6536335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(asi); 6546335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick); 6556335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(fprs); 6566335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(gsr); 6576335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(softint); 6586335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick_cmpr); 6596335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(stick); 6606335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(stick_cmpr); 6616335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tpc,MaxTL); 6626335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tnpc,MaxTL); 6636335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tstate,MaxTL); 6646335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tt,MaxTL); 6656335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tba); 6666335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(pstate); 6676335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tl); 6686335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(pil); 6696335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cwp); 6706335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(gl); 6716335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hpstate); 6726335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(htstate,MaxTL); 6736335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hintp); 6746335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(htba); 6756335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hstick_cmpr); 6766335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(strandStatusReg); 6776335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(fsr); 6786335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(priContext); 6796335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(secContext); 6806335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(partId); 6816335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(lsuCtrlReg); 6826335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(scratchPad,8); 6836335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cpu_mondo_head); 6846335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cpu_mondo_tail); 6856335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(dev_mondo_head); 6866335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(dev_mondo_tail); 6876335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(res_error_head); 6886335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(res_error_tail); 6896335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nres_error_head); 6906335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nres_error_tail); 6916335Sgblack@eecs.umich.edu 6926335Sgblack@eecs.umich.edu#if FULL_SYSTEM 6936335Sgblack@eecs.umich.edu Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; 6946335Sgblack@eecs.umich.edu ThreadContext *tc = NULL; 6956335Sgblack@eecs.umich.edu BaseCPU *cpu = NULL; 6966335Sgblack@eecs.umich.edu int tc_num; 6976335Sgblack@eecs.umich.edu bool tick_intr_sched; 6986335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick_intr_sched); 6996335Sgblack@eecs.umich.edu if (tick_intr_sched) { 7006335Sgblack@eecs.umich.edu UNSERIALIZE_OBJPTR(cpu); 7016335Sgblack@eecs.umich.edu if (cpu) { 7026335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tc_num); 7036335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick_cmp); 7046335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(stick_cmp); 7056335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hstick_cmp); 7066335Sgblack@eecs.umich.edu tc = cpu->getContext(tc_num); 7076335Sgblack@eecs.umich.edu 7086335Sgblack@eecs.umich.edu if (tick_cmp) { 7096335Sgblack@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 7106335Sgblack@eecs.umich.edu em->schedule(tickCompare, tick_cmp); 7116335Sgblack@eecs.umich.edu } 7126335Sgblack@eecs.umich.edu if (stick_cmp) { 7136335Sgblack@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 7146335Sgblack@eecs.umich.edu em->schedule(sTickCompare, stick_cmp); 7156335Sgblack@eecs.umich.edu } 7166335Sgblack@eecs.umich.edu if (hstick_cmp) { 7176335Sgblack@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 7186335Sgblack@eecs.umich.edu em->schedule(hSTickCompare, hstick_cmp); 7196335Sgblack@eecs.umich.edu } 7206335Sgblack@eecs.umich.edu } 7216335Sgblack@eecs.umich.edu } 7226335Sgblack@eecs.umich.edu 7236335Sgblack@eecs.umich.edu #endif 7246313Sgblack@eecs.umich.edu} 7256313Sgblack@eecs.umich.edu 7266313Sgblack@eecs.umich.eduint 7276313Sgblack@eecs.umich.eduISA::flattenIntIndex(int reg) 7286313Sgblack@eecs.umich.edu{ 7296335Sgblack@eecs.umich.edu int gl = readMiscRegNoEffect(MISCREG_GL); 7306335Sgblack@eecs.umich.edu int cwp = readMiscRegNoEffect(MISCREG_CWP); 7316313Sgblack@eecs.umich.edu //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp); 7326313Sgblack@eecs.umich.edu int newReg; 7336313Sgblack@eecs.umich.edu //The total number of global registers 7346313Sgblack@eecs.umich.edu int numGlobals = (MaxGL + 1) * 8; 7356313Sgblack@eecs.umich.edu if(reg < 8) 7366313Sgblack@eecs.umich.edu { 7376313Sgblack@eecs.umich.edu //Global register 7386313Sgblack@eecs.umich.edu //Put it in the appropriate set of globals 7396313Sgblack@eecs.umich.edu newReg = reg + gl * 8; 7406313Sgblack@eecs.umich.edu } 7416313Sgblack@eecs.umich.edu else if(reg < NumIntArchRegs) 7426313Sgblack@eecs.umich.edu { 7436313Sgblack@eecs.umich.edu //Regular windowed register 7446313Sgblack@eecs.umich.edu //Put it in the window pointed to by cwp 7456313Sgblack@eecs.umich.edu newReg = numGlobals + 7466313Sgblack@eecs.umich.edu ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16)); 7476313Sgblack@eecs.umich.edu } 7486313Sgblack@eecs.umich.edu else if(reg < NumIntArchRegs + NumMicroIntRegs) 7496313Sgblack@eecs.umich.edu { 7506313Sgblack@eecs.umich.edu //Microcode register 7516313Sgblack@eecs.umich.edu //Displace from the end of the regular registers 7526313Sgblack@eecs.umich.edu newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16; 7536313Sgblack@eecs.umich.edu } 7546313Sgblack@eecs.umich.edu else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs) 7556313Sgblack@eecs.umich.edu { 7566313Sgblack@eecs.umich.edu reg -= (NumIntArchRegs + NumMicroIntRegs); 7576313Sgblack@eecs.umich.edu if(reg < 8) 7586313Sgblack@eecs.umich.edu { 7596313Sgblack@eecs.umich.edu //Global register from the next window 7606313Sgblack@eecs.umich.edu //Put it in the appropriate set of globals 7616313Sgblack@eecs.umich.edu newReg = reg + gl * 8; 7626313Sgblack@eecs.umich.edu } 7636313Sgblack@eecs.umich.edu else 7646313Sgblack@eecs.umich.edu { 7656313Sgblack@eecs.umich.edu //Windowed register from the previous window 7666313Sgblack@eecs.umich.edu //Put it in the window before the one pointed to by cwp 7676313Sgblack@eecs.umich.edu newReg = numGlobals + 7686313Sgblack@eecs.umich.edu ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16)); 7696313Sgblack@eecs.umich.edu } 7706313Sgblack@eecs.umich.edu } 7716313Sgblack@eecs.umich.edu else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs) 7726313Sgblack@eecs.umich.edu { 7736313Sgblack@eecs.umich.edu reg -= (2 * NumIntArchRegs + NumMicroIntRegs); 7746313Sgblack@eecs.umich.edu if(reg < 8) 7756313Sgblack@eecs.umich.edu { 7766313Sgblack@eecs.umich.edu //Global register from the previous window 7776313Sgblack@eecs.umich.edu //Put it in the appropriate set of globals 7786313Sgblack@eecs.umich.edu newReg = reg + gl * 8; 7796313Sgblack@eecs.umich.edu } 7806313Sgblack@eecs.umich.edu else 7816313Sgblack@eecs.umich.edu { 7826313Sgblack@eecs.umich.edu //Windowed register from the next window 7836313Sgblack@eecs.umich.edu //Put it in the window after the one pointed to by cwp 7846313Sgblack@eecs.umich.edu newReg = numGlobals + 7856313Sgblack@eecs.umich.edu ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16)); 7866313Sgblack@eecs.umich.edu } 7876313Sgblack@eecs.umich.edu } 7886313Sgblack@eecs.umich.edu else 7896313Sgblack@eecs.umich.edu panic("Tried to flatten invalid register index %d!\n", reg); 7906313Sgblack@eecs.umich.edu DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg); 7916313Sgblack@eecs.umich.edu return newReg; 7926313Sgblack@eecs.umich.edu} 7936313Sgblack@eecs.umich.edu 7946313Sgblack@eecs.umich.edu} 795