xref: /gem5/src/arch/sparc/isa.cc

/*
 * Copyright (c) 2009 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Gabe Black
 */

#include "arch/sparc/isa.hh"
#include "cpu/thread_context.hh"

namespace SparcISA
{

void
ISA::clear()
{
    miscRegFile.clear();
}

MiscReg
ISA::readMiscRegNoEffect(int miscReg)
{
    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
}

MiscReg
ISA::readMiscReg(int miscReg, ThreadContext *tc)
{
    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
}

void
ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
{
    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
}

void
ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
{
    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
}

int
ISA::flattenIntIndex(int reg)
{
    int gl = miscRegFile.readRegNoEffect(MISCREG_GL);
    int cwp = miscRegFile.readRegNoEffect(MISCREG_CWP);
    //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
    int newReg;
    //The total number of global registers
    int numGlobals = (MaxGL + 1) * 8;
    if(reg < 8)
    {
        //Global register
        //Put it in the appropriate set of globals
        newReg = reg + gl * 8;
    }
    else if(reg < NumIntArchRegs)
    {
        //Regular windowed register
        //Put it in the window pointed to by cwp
        newReg = numGlobals +
            ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
    }
    else if(reg < NumIntArchRegs + NumMicroIntRegs)
    {
        //Microcode register
        //Displace from the end of the regular registers
        newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
    }
    else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
    {
        reg -= (NumIntArchRegs + NumMicroIntRegs);
        if(reg < 8)
        {
            //Global register from the next window
            //Put it in the appropriate set of globals
            newReg = reg + gl * 8;
        }
        else
        {
            //Windowed register from the previous window
            //Put it in the window before the one pointed to by cwp
            newReg = numGlobals +
                ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
        }
    }
    else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
    {
        reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
        if(reg < 8)
        {
            //Global register from the previous window
            //Put it in the appropriate set of globals
            newReg = reg + gl * 8;
        }
        else
        {
            //Windowed register from the next window
            //Put it in the window after the one pointed to by cwp
            newReg = numGlobals +
                ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
        }
    }
    else
        panic("Tried to flatten invalid register index %d!\n", reg);
    DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg);
    return newReg;
}

void
ISA::serialize(EventManager *em, std::ostream &os)
{
    miscRegFile.serialize(em, os);
}

void
ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
{
    miscRegFile.unserialize(em, cp, section);
}

}