interrupts.hh revision 5810:606de5b3d116 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Lisa Hsu
30 */
31
32#ifndef __ARCH_SPARC_INTERRUPT_HH__
33#define __ARCH_SPARC_INTERRUPT_HH__
34
35#include "arch/sparc/faults.hh"
36#include "arch/sparc/isa_traits.hh"
37#include "cpu/thread_context.hh"
38#include "params/SparcInterrupts.hh"
39#include "sim/sim_object.hh"
40
41namespace SparcISA
42{
43
44class Interrupts : public SimObject
45{
46  private:
47    BaseCPU * cpu;
48
49    uint64_t interrupts[NumInterruptTypes];
50    uint64_t intStatus;
51
52  public:
53
54    void
55    setCPU(BaseCPU * _cpu)
56    {
57        cpu = _cpu;
58    }
59
60    typedef SparcInterruptsParams Params;
61
62    const Params *
63    params() const
64    {
65        return dynamic_cast<const Params *>(_params);
66    }
67
68    Interrupts(Params * p) : SimObject(p), cpu(NULL)
69    {
70        clearAll();
71    }
72
73    int
74    InterruptLevel(uint64_t softint)
75    {
76        if (softint & 0x10000 || softint & 0x1)
77            return 14;
78
79        int level = 15;
80        while (level > 0 && !(1 << level & softint))
81            level--;
82        if (1 << level & softint)
83            return level;
84        return 0;
85    }
86
87    void
88    post(int int_num, int index)
89    {
90        DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
91        assert(int_num >= 0 && int_num < NumInterruptTypes);
92        assert(index >= 0 && index < 64);
93
94        interrupts[int_num] |= ULL(1) << index;
95        intStatus |= ULL(1) << int_num;
96    }
97
98    void
99    clear(int int_num, int index)
100    {
101        DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
102        assert(int_num >= 0 && int_num < NumInterruptTypes);
103        assert(index >= 0 && index < 64);
104
105        interrupts[int_num] &= ~(ULL(1) << index);
106        if (!interrupts[int_num])
107            intStatus &= ~(ULL(1) << int_num);
108    }
109
110    void
111    clearAll()
112    {
113        for (int i = 0; i < NumInterruptTypes; ++i) {
114            interrupts[i] = 0;
115        }
116        intStatus = 0;
117    }
118
119    bool
120    checkInterrupts(ThreadContext *tc) const
121    {
122        return intStatus;
123    }
124
125    Fault
126    getInterrupt(ThreadContext *tc)
127    {
128        int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
129        int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
130        bool ie = pstate & PSTATE::ie;
131
132        // THESE ARE IN ORDER OF PRIORITY
133        // since there are early returns, and the highest
134        // priority interrupts should get serviced,
135        // it is v. important that new interrupts are inserted
136        // in the right order of processing
137        if (hpstate & HPSTATE::hpriv) {
138            if (ie) {
139                if (interrupts[IT_HINTP]) {
140                    // This will be cleaned by a HINTP write
141                    return new HstickMatch;
142                }
143                if (interrupts[IT_INT_VEC]) {
144                    // this will be cleared by an ASI read (or write)
145                    return new InterruptVector;
146                }
147            }
148        } else {
149            if (interrupts[IT_TRAP_LEVEL_ZERO]) {
150                    // this is cleared by deasserting HPSTATE::tlz
151                    return new TrapLevelZero;
152            }
153            // HStick matches always happen in priv mode (ie doesn't matter)
154            if (interrupts[IT_HINTP]) {
155                return new HstickMatch;
156            }
157            if (interrupts[IT_INT_VEC]) {
158                // this will be cleared by an ASI read (or write)
159                return new InterruptVector;
160            }
161            if (ie) {
162                if (interrupts[IT_CPU_MONDO]) {
163                    return new CpuMondo;
164                }
165                if (interrupts[IT_DEV_MONDO]) {
166                    return new DevMondo;
167                }
168                if (interrupts[IT_SOFT_INT]) {
169                    int level = InterruptLevel(interrupts[IT_SOFT_INT]);
170                    return new InterruptLevelN(level);
171                }
172
173                if (interrupts[IT_RES_ERROR]) {
174                    return new ResumableError;
175                }
176            } // !hpriv && ie
177        }  // !hpriv
178        return NoFault;
179    }
180
181    void
182    updateIntrInfo(ThreadContext *tc)
183    {
184
185    }
186
187    uint64_t
188    get_vec(int int_num)
189    {
190        assert(int_num >= 0 && int_num < NumInterruptTypes);
191        return interrupts[int_num];
192    }
193
194    void
195    serialize(std::ostream &os)
196    {
197        SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
198        SERIALIZE_SCALAR(intStatus);
199    }
200
201    void
202    unserialize(Checkpoint *cp, const std::string &section)
203    {
204        UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
205        UNSERIALIZE_SCALAR(intStatus);
206    }
207};
208} // namespace SPARC_ISA
209
210#endif // __ARCH_SPARC_INTERRUPT_HH__
211