interrupts.hh revision 3896:182be4779097
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_SPARC_INTERRUPT_HH__ 30#define __ARCH_SPARC_INTERRUPT_HH__ 31 32#include "arch/sparc/faults.hh" 33#include "cpu/thread_context.hh" 34 35namespace SparcISA 36{ 37 38enum interrupts_t { 39 trap_level_zero, 40 hstick_match, 41 interrupt_vector, 42 cpu_mondo, 43 dev_mondo, 44 resumable_error, 45 soft_interrupt, 46 num_interrupt_types 47}; 48 49 class Interrupts 50 { 51 52 private: 53 54 bool interrupts[num_interrupt_types]; 55 int numPosted; 56 57 public: 58 Interrupts() 59 { 60 for (int i = 0; i < num_interrupt_types; ++i) { 61 interrupts[i] = false; 62 } 63 numPosted = 0; 64 } 65 66 void post(int int_type) 67 { 68 if (int_type < 0 || int_type >= num_interrupt_types) 69 panic("posting unknown interrupt!\n"); 70 interrupts[int_type] = true; 71 ++numPosted; 72 } 73 74 void post(int int_num, int index) 75 { 76 77 } 78 79 void clear(int int_num, int index) 80 { 81 82 } 83 84 void clear_all() 85 { 86 87 } 88 89 bool check_interrupts(ThreadContext * tc) const 90 { 91 if (numPosted) 92 return true; 93 else 94 return false; 95 } 96 97 Fault getInterrupt(ThreadContext * tc) 98 { 99 int hpstate = tc->readMiscReg(MISCREG_HPSTATE); 100 int pstate = tc->readMiscReg(MISCREG_PSTATE); 101 bool ie = pstate & PSTATE::ie; 102 103 // THESE ARE IN ORDER OF PRIORITY 104 // since there are early returns, and the highest 105 // priority interrupts should get serviced, 106 // it is v. important that new interrupts are inserted 107 // in the right order of processing 108 if (hpstate & HPSTATE::hpriv) { 109 if (ie) { 110 if (interrupts[hstick_match]) { 111 interrupts[hstick_match] = false; 112 --numPosted; 113 return new HstickMatch; 114 } 115 if (interrupts[interrupt_vector]) { 116 interrupts[interrupt_vector] = false; 117 --numPosted; 118 //HAVEN'T IMPLed THIS YET 119 return NoFault; 120 } 121 } 122 } else { 123 124 if (interrupts[trap_level_zero]) { 125 if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) { 126 interrupts[trap_level_zero] = false; 127 --numPosted; 128 return new TrapLevelZero; 129 } 130 } 131 if (interrupts[hstick_match]) { 132 interrupts[hstick_match] = false; 133 --numPosted; 134 return new HstickMatch; 135 } 136 if (ie) { 137 if (interrupts[cpu_mondo]) { 138 interrupts[cpu_mondo] = false; 139 --numPosted; 140 return new CpuMondo; 141 } 142 if (interrupts[dev_mondo]) { 143 interrupts[dev_mondo] = false; 144 --numPosted; 145 return new DevMondo; 146 } 147 if (interrupts[soft_interrupt]) { 148 int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); 149 // it seems that interrupt vectors are right in 150 // the middle of interrupt levels with regard to 151 // priority, so have to check 152 if ((il < 6) && 153 interrupts[interrupt_vector]) { 154 // may require more details here since there 155 // may be lots of interrupts embedded in an 156 // platform interrupt vector 157 interrupts[interrupt_vector] = false; 158 --numPosted; 159 //HAVEN'T IMPLed YET 160 return NoFault; 161 } else { 162 if (il > tc->readMiscReg(MISCREG_PIL)) { 163 uint64_t si = tc->readMiscReg(MISCREG_SOFTINT); 164 uint64_t more = si & ~(1 << (il + 1)); 165 if (!InterruptLevel(more)) { 166 interrupts[soft_interrupt] = false; 167 --numPosted; 168 } 169 return new InterruptLevelN(il); 170 } 171 } 172 } 173 if (interrupts[resumable_error]) { 174 interrupts[resumable_error] = false; 175 --numPosted; 176 return new ResumableError; 177 } 178 } 179 } 180 return NoFault; 181 } 182 183 void updateIntrInfo(ThreadContext * tc) 184 { 185 186 } 187 188 void serialize(std::ostream &os) 189 { 190 } 191 192 void unserialize(Checkpoint *cp, const std::string §ion) 193 { 194 } 195 }; 196} 197 198#endif // __ARCH_SPARC_INTERRUPT_HH__ 199