interrupts.hh revision 11566:b11410957c9e 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Lisa Hsu
30 */
31
32#ifndef __ARCH_SPARC_INTERRUPT_HH__
33#define __ARCH_SPARC_INTERRUPT_HH__
34
35#include "arch/sparc/faults.hh"
36#include "arch/sparc/isa_traits.hh"
37#include "arch/sparc/registers.hh"
38#include "cpu/thread_context.hh"
39#include "debug/Interrupt.hh"
40#include "params/SparcInterrupts.hh"
41#include "sim/sim_object.hh"
42
43namespace SparcISA
44{
45
46class Interrupts : public SimObject
47{
48  private:
49    BaseCPU * cpu;
50
51    uint64_t interrupts[NumInterruptTypes];
52    uint64_t intStatus;
53
54  public:
55
56    void
57    setCPU(BaseCPU * _cpu)
58    {
59        cpu = _cpu;
60    }
61
62    typedef SparcInterruptsParams Params;
63
64    const Params *
65    params() const
66    {
67        return dynamic_cast<const Params *>(_params);
68    }
69
70    Interrupts(Params * p) : SimObject(p), cpu(NULL)
71    {
72        clearAll();
73    }
74
75    int
76    InterruptLevel(uint64_t softint)
77    {
78        if (softint & 0x10000 || softint & 0x1)
79            return 14;
80
81        int level = 15;
82        while (level > 0 && !(1 << level & softint))
83            level--;
84        if (1 << level & softint)
85            return level;
86        return 0;
87    }
88
89    void
90    post(int int_num, int index)
91    {
92        DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
93        assert(int_num >= 0 && int_num < NumInterruptTypes);
94        assert(index >= 0 && index < 64);
95
96        interrupts[int_num] |= ULL(1) << index;
97        intStatus |= ULL(1) << int_num;
98    }
99
100    void
101    clear(int int_num, int index)
102    {
103        DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
104        assert(int_num >= 0 && int_num < NumInterruptTypes);
105        assert(index >= 0 && index < 64);
106
107        interrupts[int_num] &= ~(ULL(1) << index);
108        if (!interrupts[int_num])
109            intStatus &= ~(ULL(1) << int_num);
110    }
111
112    void
113    clearAll()
114    {
115        for (int i = 0; i < NumInterruptTypes; ++i) {
116            interrupts[i] = 0;
117        }
118        intStatus = 0;
119    }
120
121    bool
122    checkInterrupts(ThreadContext *tc) const
123    {
124        if (!intStatus)
125            return false;
126
127        HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
128        PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
129
130        // THESE ARE IN ORDER OF PRIORITY
131        // since there are early returns, and the highest
132        // priority interrupts should get serviced,
133        // it is v. important that new interrupts are inserted
134        // in the right order of processing
135        if (hpstate.hpriv) {
136            if (pstate.ie) {
137                if (interrupts[IT_HINTP]) {
138                    // This will be cleaned by a HINTP write
139                    return true;
140                }
141                if (interrupts[IT_INT_VEC]) {
142                    // this will be cleared by an ASI read (or write)
143                    return true;
144                }
145            }
146        } else {
147            if (interrupts[IT_TRAP_LEVEL_ZERO]) {
148                    // this is cleared by deasserting HPSTATE::tlz
149                return true;
150            }
151            // HStick matches always happen in priv mode (ie doesn't matter)
152            if (interrupts[IT_HINTP]) {
153                return true;
154            }
155            if (interrupts[IT_INT_VEC]) {
156                // this will be cleared by an ASI read (or write)
157                return true;
158            }
159            if (pstate.ie) {
160                if (interrupts[IT_CPU_MONDO]) {
161                    return true;
162                }
163                if (interrupts[IT_DEV_MONDO]) {
164                    return true;
165                }
166                if (interrupts[IT_SOFT_INT]) {
167                    return true;
168                }
169
170                if (interrupts[IT_RES_ERROR]) {
171                    return true;
172                }
173            } // !hpriv && pstate.ie
174        }  // !hpriv
175
176        return false;
177    }
178
179    Fault
180    getInterrupt(ThreadContext *tc)
181    {
182        assert(checkInterrupts(tc));
183
184        HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
185        PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
186
187        // THESE ARE IN ORDER OF PRIORITY
188        // since there are early returns, and the highest
189        // priority interrupts should get serviced,
190        // it is v. important that new interrupts are inserted
191        // in the right order of processing
192        if (hpstate.hpriv) {
193            if (pstate.ie) {
194                if (interrupts[IT_HINTP]) {
195                    // This will be cleaned by a HINTP write
196                    return std::make_shared<HstickMatch>();
197                }
198                if (interrupts[IT_INT_VEC]) {
199                    // this will be cleared by an ASI read (or write)
200                    return std::make_shared<InterruptVector>();
201                }
202            }
203        } else {
204            if (interrupts[IT_TRAP_LEVEL_ZERO]) {
205                    // this is cleared by deasserting HPSTATE::tlz
206                return std::make_shared<TrapLevelZero>();
207            }
208            // HStick matches always happen in priv mode (ie doesn't matter)
209            if (interrupts[IT_HINTP]) {
210                return std::make_shared<HstickMatch>();
211            }
212            if (interrupts[IT_INT_VEC]) {
213                // this will be cleared by an ASI read (or write)
214                return std::make_shared<InterruptVector>();
215            }
216            if (pstate.ie) {
217                if (interrupts[IT_CPU_MONDO]) {
218                    return std::make_shared<CpuMondo>();
219                }
220                if (interrupts[IT_DEV_MONDO]) {
221                    return std::make_shared<DevMondo>();
222                }
223                if (interrupts[IT_SOFT_INT]) {
224                    int level = InterruptLevel(interrupts[IT_SOFT_INT]);
225                    return std::make_shared<InterruptLevelN>(level);
226                }
227
228                if (interrupts[IT_RES_ERROR]) {
229                    return std::make_shared<ResumableError>();
230                }
231            } // !hpriv && pstate.ie
232        }  // !hpriv
233        return NoFault;
234    }
235
236    void
237    updateIntrInfo(ThreadContext *tc)
238    {}
239
240    uint64_t
241    get_vec(int int_num)
242    {
243        assert(int_num >= 0 && int_num < NumInterruptTypes);
244        return interrupts[int_num];
245    }
246
247    void
248    serialize(CheckpointOut &cp) const override
249    {
250        SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
251        SERIALIZE_SCALAR(intStatus);
252    }
253
254    void
255    unserialize(CheckpointIn &cp) override
256    {
257        UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
258        UNSERIALIZE_SCALAR(intStatus);
259    }
260};
261} // namespace SPARC_ISA
262
263#endif // __ARCH_SPARC_INTERRUPT_HH__
264