interrupts.hh revision 6335
13537Sgblack@eecs.umich.edu/* 23537Sgblack@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 33537Sgblack@eecs.umich.edu * All rights reserved. 43537Sgblack@eecs.umich.edu * 53537Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63537Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73537Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83537Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93537Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103537Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113537Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123537Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133537Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143537Sgblack@eecs.umich.edu * this software without specific prior written permission. 153537Sgblack@eecs.umich.edu * 163537Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173537Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183537Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193537Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203537Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213537Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223537Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233537Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243537Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253537Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263537Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274103Ssaidi@eecs.umich.edu * 284103Ssaidi@eecs.umich.edu * Authors: Ali Saidi 294103Ssaidi@eecs.umich.edu * Lisa Hsu 303537Sgblack@eecs.umich.edu */ 313537Sgblack@eecs.umich.edu 323537Sgblack@eecs.umich.edu#ifndef __ARCH_SPARC_INTERRUPT_HH__ 333537Sgblack@eecs.umich.edu#define __ARCH_SPARC_INTERRUPT_HH__ 343537Sgblack@eecs.umich.edu 353537Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 364103Ssaidi@eecs.umich.edu#include "arch/sparc/isa_traits.hh" 376335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 383827Shsul@eecs.umich.edu#include "cpu/thread_context.hh" 395647Sgblack@eecs.umich.edu#include "params/SparcInterrupts.hh" 405647Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 413827Shsul@eecs.umich.edu 423537Sgblack@eecs.umich.edunamespace SparcISA 433537Sgblack@eecs.umich.edu{ 443894Shsul@eecs.umich.edu 455647Sgblack@eecs.umich.educlass Interrupts : public SimObject 464009Ssaidi@eecs.umich.edu{ 475810Sgblack@eecs.umich.edu private: 485810Sgblack@eecs.umich.edu BaseCPU * cpu; 494009Ssaidi@eecs.umich.edu 504103Ssaidi@eecs.umich.edu uint64_t interrupts[NumInterruptTypes]; 514103Ssaidi@eecs.umich.edu uint64_t intStatus; 524009Ssaidi@eecs.umich.edu 534009Ssaidi@eecs.umich.edu public: 545810Sgblack@eecs.umich.edu 555810Sgblack@eecs.umich.edu void 565810Sgblack@eecs.umich.edu setCPU(BaseCPU * _cpu) 575810Sgblack@eecs.umich.edu { 585810Sgblack@eecs.umich.edu cpu = _cpu; 595810Sgblack@eecs.umich.edu } 605810Sgblack@eecs.umich.edu 615647Sgblack@eecs.umich.edu typedef SparcInterruptsParams Params; 625647Sgblack@eecs.umich.edu 635647Sgblack@eecs.umich.edu const Params * 645647Sgblack@eecs.umich.edu params() const 655647Sgblack@eecs.umich.edu { 665647Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 675647Sgblack@eecs.umich.edu } 685647Sgblack@eecs.umich.edu 695810Sgblack@eecs.umich.edu Interrupts(Params * p) : SimObject(p), cpu(NULL) 704009Ssaidi@eecs.umich.edu { 715704Snate@binkert.org clearAll(); 724009Ssaidi@eecs.umich.edu } 734009Ssaidi@eecs.umich.edu 745704Snate@binkert.org int 755704Snate@binkert.org InterruptLevel(uint64_t softint) 764009Ssaidi@eecs.umich.edu { 774103Ssaidi@eecs.umich.edu if (softint & 0x10000 || softint & 0x1) 784103Ssaidi@eecs.umich.edu return 14; 794103Ssaidi@eecs.umich.edu 804103Ssaidi@eecs.umich.edu int level = 15; 814103Ssaidi@eecs.umich.edu while (level > 0 && !(1 << level & softint)) 824103Ssaidi@eecs.umich.edu level--; 834103Ssaidi@eecs.umich.edu if (1 << level & softint) 844103Ssaidi@eecs.umich.edu return level; 854103Ssaidi@eecs.umich.edu return 0; 864009Ssaidi@eecs.umich.edu } 874009Ssaidi@eecs.umich.edu 885704Snate@binkert.org void 895704Snate@binkert.org post(int int_num, int index) 903537Sgblack@eecs.umich.edu { 914103Ssaidi@eecs.umich.edu DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 924103Ssaidi@eecs.umich.edu assert(int_num >= 0 && int_num < NumInterruptTypes); 934103Ssaidi@eecs.umich.edu assert(index >= 0 && index < 64); 943827Shsul@eecs.umich.edu 954103Ssaidi@eecs.umich.edu interrupts[int_num] |= ULL(1) << index; 964103Ssaidi@eecs.umich.edu intStatus |= ULL(1) << int_num; 974009Ssaidi@eecs.umich.edu } 983894Shsul@eecs.umich.edu 995704Snate@binkert.org void 1005704Snate@binkert.org clear(int int_num, int index) 1014009Ssaidi@eecs.umich.edu { 1024103Ssaidi@eecs.umich.edu DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 1034103Ssaidi@eecs.umich.edu assert(int_num >= 0 && int_num < NumInterruptTypes); 1044103Ssaidi@eecs.umich.edu assert(index >= 0 && index < 64); 1053537Sgblack@eecs.umich.edu 1064103Ssaidi@eecs.umich.edu interrupts[int_num] &= ~(ULL(1) << index); 1074103Ssaidi@eecs.umich.edu if (!interrupts[int_num]) 1084103Ssaidi@eecs.umich.edu intStatus &= ~(ULL(1) << int_num); 1094009Ssaidi@eecs.umich.edu } 1103827Shsul@eecs.umich.edu 1115704Snate@binkert.org void 1125704Snate@binkert.org clearAll() 1134009Ssaidi@eecs.umich.edu { 1144103Ssaidi@eecs.umich.edu for (int i = 0; i < NumInterruptTypes; ++i) { 1154103Ssaidi@eecs.umich.edu interrupts[i] = 0; 1164103Ssaidi@eecs.umich.edu } 1174103Ssaidi@eecs.umich.edu intStatus = 0; 1184009Ssaidi@eecs.umich.edu } 1193537Sgblack@eecs.umich.edu 1205704Snate@binkert.org bool 1215704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1224009Ssaidi@eecs.umich.edu { 1234103Ssaidi@eecs.umich.edu return intStatus; 1244009Ssaidi@eecs.umich.edu } 1253537Sgblack@eecs.umich.edu 1265704Snate@binkert.org Fault 1275704Snate@binkert.org getInterrupt(ThreadContext *tc) 1284009Ssaidi@eecs.umich.edu { 1294172Ssaidi@eecs.umich.edu int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 1304172Ssaidi@eecs.umich.edu int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 1314009Ssaidi@eecs.umich.edu bool ie = pstate & PSTATE::ie; 1323827Shsul@eecs.umich.edu 1334009Ssaidi@eecs.umich.edu // THESE ARE IN ORDER OF PRIORITY 1344009Ssaidi@eecs.umich.edu // since there are early returns, and the highest 1354009Ssaidi@eecs.umich.edu // priority interrupts should get serviced, 1364009Ssaidi@eecs.umich.edu // it is v. important that new interrupts are inserted 1374009Ssaidi@eecs.umich.edu // in the right order of processing 1384009Ssaidi@eecs.umich.edu if (hpstate & HPSTATE::hpriv) { 1394009Ssaidi@eecs.umich.edu if (ie) { 1404103Ssaidi@eecs.umich.edu if (interrupts[IT_HINTP]) { 1414103Ssaidi@eecs.umich.edu // This will be cleaned by a HINTP write 1424103Ssaidi@eecs.umich.edu return new HstickMatch; 1433894Shsul@eecs.umich.edu } 1444103Ssaidi@eecs.umich.edu if (interrupts[IT_INT_VEC]) { 1454103Ssaidi@eecs.umich.edu // this will be cleared by an ASI read (or write) 1464103Ssaidi@eecs.umich.edu return new InterruptVector; 1474009Ssaidi@eecs.umich.edu } 1484103Ssaidi@eecs.umich.edu } 1494103Ssaidi@eecs.umich.edu } else { 1504103Ssaidi@eecs.umich.edu if (interrupts[IT_TRAP_LEVEL_ZERO]) { 1514103Ssaidi@eecs.umich.edu // this is cleared by deasserting HPSTATE::tlz 1524103Ssaidi@eecs.umich.edu return new TrapLevelZero; 1534103Ssaidi@eecs.umich.edu } 1544103Ssaidi@eecs.umich.edu // HStick matches always happen in priv mode (ie doesn't matter) 1554103Ssaidi@eecs.umich.edu if (interrupts[IT_HINTP]) { 1564103Ssaidi@eecs.umich.edu return new HstickMatch; 1574103Ssaidi@eecs.umich.edu } 1584103Ssaidi@eecs.umich.edu if (interrupts[IT_INT_VEC]) { 1594103Ssaidi@eecs.umich.edu // this will be cleared by an ASI read (or write) 1604103Ssaidi@eecs.umich.edu return new InterruptVector; 1614103Ssaidi@eecs.umich.edu } 1624103Ssaidi@eecs.umich.edu if (ie) { 1634103Ssaidi@eecs.umich.edu if (interrupts[IT_CPU_MONDO]) { 1644103Ssaidi@eecs.umich.edu return new CpuMondo; 1654103Ssaidi@eecs.umich.edu } 1664103Ssaidi@eecs.umich.edu if (interrupts[IT_DEV_MONDO]) { 1674103Ssaidi@eecs.umich.edu return new DevMondo; 1684103Ssaidi@eecs.umich.edu } 1694103Ssaidi@eecs.umich.edu if (interrupts[IT_SOFT_INT]) { 1705704Snate@binkert.org int level = InterruptLevel(interrupts[IT_SOFT_INT]); 1715704Snate@binkert.org return new InterruptLevelN(level); 1724009Ssaidi@eecs.umich.edu } 1734009Ssaidi@eecs.umich.edu 1744103Ssaidi@eecs.umich.edu if (interrupts[IT_RES_ERROR]) { 1754009Ssaidi@eecs.umich.edu return new ResumableError; 1763894Shsul@eecs.umich.edu } 1774103Ssaidi@eecs.umich.edu } // !hpriv && ie 1784103Ssaidi@eecs.umich.edu } // !hpriv 1794009Ssaidi@eecs.umich.edu return NoFault; 1804009Ssaidi@eecs.umich.edu } 1813537Sgblack@eecs.umich.edu 1825704Snate@binkert.org void 1835704Snate@binkert.org updateIntrInfo(ThreadContext *tc) 1844009Ssaidi@eecs.umich.edu { 1853654Shsul@eecs.umich.edu 1864009Ssaidi@eecs.umich.edu } 1873654Shsul@eecs.umich.edu 1885704Snate@binkert.org uint64_t 1895704Snate@binkert.org get_vec(int int_num) 1904103Ssaidi@eecs.umich.edu { 1914103Ssaidi@eecs.umich.edu assert(int_num >= 0 && int_num < NumInterruptTypes); 1924103Ssaidi@eecs.umich.edu return interrupts[int_num]; 1934103Ssaidi@eecs.umich.edu } 1944103Ssaidi@eecs.umich.edu 1955704Snate@binkert.org void 1965704Snate@binkert.org serialize(std::ostream &os) 1974009Ssaidi@eecs.umich.edu { 1984103Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(interrupts,NumInterruptTypes); 1994103Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(intStatus); 2004009Ssaidi@eecs.umich.edu } 2013537Sgblack@eecs.umich.edu 2025704Snate@binkert.org void 2035704Snate@binkert.org unserialize(Checkpoint *cp, const std::string §ion) 2044009Ssaidi@eecs.umich.edu { 2054103Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes); 2064103Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(intStatus); 2074009Ssaidi@eecs.umich.edu } 2084009Ssaidi@eecs.umich.edu}; 2094009Ssaidi@eecs.umich.edu} // namespace SPARC_ISA 2103537Sgblack@eecs.umich.edu 2113537Sgblack@eecs.umich.edu#endif // __ARCH_SPARC_INTERRUPT_HH__ 212