interrupts.hh revision 3896
13537Sgblack@eecs.umich.edu/* 23537Sgblack@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 33537Sgblack@eecs.umich.edu * All rights reserved. 43537Sgblack@eecs.umich.edu * 53537Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63537Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73537Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83537Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93537Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103537Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113537Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123537Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133537Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143537Sgblack@eecs.umich.edu * this software without specific prior written permission. 153537Sgblack@eecs.umich.edu * 163537Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173537Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183537Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193537Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203537Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213537Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223537Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233537Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243537Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253537Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263537Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273537Sgblack@eecs.umich.edu */ 283537Sgblack@eecs.umich.edu 293537Sgblack@eecs.umich.edu#ifndef __ARCH_SPARC_INTERRUPT_HH__ 303537Sgblack@eecs.umich.edu#define __ARCH_SPARC_INTERRUPT_HH__ 313537Sgblack@eecs.umich.edu 323537Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 333827Shsul@eecs.umich.edu#include "cpu/thread_context.hh" 343827Shsul@eecs.umich.edu 353537Sgblack@eecs.umich.edunamespace SparcISA 363537Sgblack@eecs.umich.edu{ 373894Shsul@eecs.umich.edu 383894Shsul@eecs.umich.eduenum interrupts_t { 393894Shsul@eecs.umich.edu trap_level_zero, 403894Shsul@eecs.umich.edu hstick_match, 413894Shsul@eecs.umich.edu interrupt_vector, 423894Shsul@eecs.umich.edu cpu_mondo, 433894Shsul@eecs.umich.edu dev_mondo, 443894Shsul@eecs.umich.edu resumable_error, 453894Shsul@eecs.umich.edu soft_interrupt, 463894Shsul@eecs.umich.edu num_interrupt_types 473894Shsul@eecs.umich.edu}; 483894Shsul@eecs.umich.edu 493537Sgblack@eecs.umich.edu class Interrupts 503537Sgblack@eecs.umich.edu { 513827Shsul@eecs.umich.edu 523894Shsul@eecs.umich.edu private: 533894Shsul@eecs.umich.edu 543894Shsul@eecs.umich.edu bool interrupts[num_interrupt_types]; 553894Shsul@eecs.umich.edu int numPosted; 563537Sgblack@eecs.umich.edu 573537Sgblack@eecs.umich.edu public: 583537Sgblack@eecs.umich.edu Interrupts() 593537Sgblack@eecs.umich.edu { 603894Shsul@eecs.umich.edu for (int i = 0; i < num_interrupt_types; ++i) { 613894Shsul@eecs.umich.edu interrupts[i] = false; 623894Shsul@eecs.umich.edu } 633894Shsul@eecs.umich.edu numPosted = 0; 643894Shsul@eecs.umich.edu } 653827Shsul@eecs.umich.edu 663894Shsul@eecs.umich.edu void post(int int_type) 673894Shsul@eecs.umich.edu { 683894Shsul@eecs.umich.edu if (int_type < 0 || int_type >= num_interrupt_types) 693894Shsul@eecs.umich.edu panic("posting unknown interrupt!\n"); 703894Shsul@eecs.umich.edu interrupts[int_type] = true; 713894Shsul@eecs.umich.edu ++numPosted; 723537Sgblack@eecs.umich.edu } 733894Shsul@eecs.umich.edu 743537Sgblack@eecs.umich.edu void post(int int_num, int index) 753537Sgblack@eecs.umich.edu { 763537Sgblack@eecs.umich.edu 773537Sgblack@eecs.umich.edu } 783537Sgblack@eecs.umich.edu 793537Sgblack@eecs.umich.edu void clear(int int_num, int index) 803537Sgblack@eecs.umich.edu { 813827Shsul@eecs.umich.edu 823537Sgblack@eecs.umich.edu } 833537Sgblack@eecs.umich.edu 843537Sgblack@eecs.umich.edu void clear_all() 853537Sgblack@eecs.umich.edu { 863827Shsul@eecs.umich.edu 873537Sgblack@eecs.umich.edu } 883537Sgblack@eecs.umich.edu 893537Sgblack@eecs.umich.edu bool check_interrupts(ThreadContext * tc) const 903537Sgblack@eecs.umich.edu { 913894Shsul@eecs.umich.edu if (numPosted) 923827Shsul@eecs.umich.edu return true; 933827Shsul@eecs.umich.edu else 943827Shsul@eecs.umich.edu return false; 953537Sgblack@eecs.umich.edu } 963537Sgblack@eecs.umich.edu 973537Sgblack@eecs.umich.edu Fault getInterrupt(ThreadContext * tc) 983537Sgblack@eecs.umich.edu { 993894Shsul@eecs.umich.edu int hpstate = tc->readMiscReg(MISCREG_HPSTATE); 1003894Shsul@eecs.umich.edu int pstate = tc->readMiscReg(MISCREG_PSTATE); 1013894Shsul@eecs.umich.edu bool ie = pstate & PSTATE::ie; 1023894Shsul@eecs.umich.edu 1033894Shsul@eecs.umich.edu // THESE ARE IN ORDER OF PRIORITY 1043894Shsul@eecs.umich.edu // since there are early returns, and the highest 1053894Shsul@eecs.umich.edu // priority interrupts should get serviced, 1063894Shsul@eecs.umich.edu // it is v. important that new interrupts are inserted 1073894Shsul@eecs.umich.edu // in the right order of processing 1083894Shsul@eecs.umich.edu if (hpstate & HPSTATE::hpriv) { 1093894Shsul@eecs.umich.edu if (ie) { 1103894Shsul@eecs.umich.edu if (interrupts[hstick_match]) { 1113894Shsul@eecs.umich.edu interrupts[hstick_match] = false; 1123894Shsul@eecs.umich.edu --numPosted; 1133894Shsul@eecs.umich.edu return new HstickMatch; 1143894Shsul@eecs.umich.edu } 1153894Shsul@eecs.umich.edu if (interrupts[interrupt_vector]) { 1163894Shsul@eecs.umich.edu interrupts[interrupt_vector] = false; 1173894Shsul@eecs.umich.edu --numPosted; 1183894Shsul@eecs.umich.edu //HAVEN'T IMPLed THIS YET 1193894Shsul@eecs.umich.edu return NoFault; 1203894Shsul@eecs.umich.edu } 1213894Shsul@eecs.umich.edu } 1223894Shsul@eecs.umich.edu } else { 1233894Shsul@eecs.umich.edu 1243894Shsul@eecs.umich.edu if (interrupts[trap_level_zero]) { 1253894Shsul@eecs.umich.edu if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) { 1263894Shsul@eecs.umich.edu interrupts[trap_level_zero] = false; 1273894Shsul@eecs.umich.edu --numPosted; 1283896Shsul@eecs.umich.edu return new TrapLevelZero; 1293894Shsul@eecs.umich.edu } 1303894Shsul@eecs.umich.edu } 1313894Shsul@eecs.umich.edu if (interrupts[hstick_match]) { 1323894Shsul@eecs.umich.edu interrupts[hstick_match] = false; 1333894Shsul@eecs.umich.edu --numPosted; 1343894Shsul@eecs.umich.edu return new HstickMatch; 1353894Shsul@eecs.umich.edu } 1363894Shsul@eecs.umich.edu if (ie) { 1373894Shsul@eecs.umich.edu if (interrupts[cpu_mondo]) { 1383894Shsul@eecs.umich.edu interrupts[cpu_mondo] = false; 1393894Shsul@eecs.umich.edu --numPosted; 1403894Shsul@eecs.umich.edu return new CpuMondo; 1413894Shsul@eecs.umich.edu } 1423894Shsul@eecs.umich.edu if (interrupts[dev_mondo]) { 1433894Shsul@eecs.umich.edu interrupts[dev_mondo] = false; 1443894Shsul@eecs.umich.edu --numPosted; 1453894Shsul@eecs.umich.edu return new DevMondo; 1463894Shsul@eecs.umich.edu } 1473894Shsul@eecs.umich.edu if (interrupts[soft_interrupt]) { 1483894Shsul@eecs.umich.edu int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); 1493894Shsul@eecs.umich.edu // it seems that interrupt vectors are right in 1503894Shsul@eecs.umich.edu // the middle of interrupt levels with regard to 1513894Shsul@eecs.umich.edu // priority, so have to check 1523894Shsul@eecs.umich.edu if ((il < 6) && 1533894Shsul@eecs.umich.edu interrupts[interrupt_vector]) { 1543894Shsul@eecs.umich.edu // may require more details here since there 1553894Shsul@eecs.umich.edu // may be lots of interrupts embedded in an 1563894Shsul@eecs.umich.edu // platform interrupt vector 1573894Shsul@eecs.umich.edu interrupts[interrupt_vector] = false; 1583894Shsul@eecs.umich.edu --numPosted; 1593894Shsul@eecs.umich.edu //HAVEN'T IMPLed YET 1603894Shsul@eecs.umich.edu return NoFault; 1613894Shsul@eecs.umich.edu } else { 1623894Shsul@eecs.umich.edu if (il > tc->readMiscReg(MISCREG_PIL)) { 1633894Shsul@eecs.umich.edu uint64_t si = tc->readMiscReg(MISCREG_SOFTINT); 1643894Shsul@eecs.umich.edu uint64_t more = si & ~(1 << (il + 1)); 1653894Shsul@eecs.umich.edu if (!InterruptLevel(more)) { 1663894Shsul@eecs.umich.edu interrupts[soft_interrupt] = false; 1673894Shsul@eecs.umich.edu --numPosted; 1683894Shsul@eecs.umich.edu } 1693894Shsul@eecs.umich.edu return new InterruptLevelN(il); 1703894Shsul@eecs.umich.edu } 1713894Shsul@eecs.umich.edu } 1723894Shsul@eecs.umich.edu } 1733894Shsul@eecs.umich.edu if (interrupts[resumable_error]) { 1743894Shsul@eecs.umich.edu interrupts[resumable_error] = false; 1753894Shsul@eecs.umich.edu --numPosted; 1763894Shsul@eecs.umich.edu return new ResumableError; 1773894Shsul@eecs.umich.edu } 1783894Shsul@eecs.umich.edu } 1793894Shsul@eecs.umich.edu } 1803894Shsul@eecs.umich.edu return NoFault; 1813537Sgblack@eecs.umich.edu } 1823537Sgblack@eecs.umich.edu 1833654Shsul@eecs.umich.edu void updateIntrInfo(ThreadContext * tc) 1843654Shsul@eecs.umich.edu { 1853654Shsul@eecs.umich.edu 1863654Shsul@eecs.umich.edu } 1873654Shsul@eecs.umich.edu 1883537Sgblack@eecs.umich.edu void serialize(std::ostream &os) 1893537Sgblack@eecs.umich.edu { 1903537Sgblack@eecs.umich.edu } 1913537Sgblack@eecs.umich.edu 1923537Sgblack@eecs.umich.edu void unserialize(Checkpoint *cp, const std::string §ion) 1933537Sgblack@eecs.umich.edu { 1943537Sgblack@eecs.umich.edu } 1953537Sgblack@eecs.umich.edu }; 1963537Sgblack@eecs.umich.edu} 1973537Sgblack@eecs.umich.edu 1983537Sgblack@eecs.umich.edu#endif // __ARCH_SPARC_INTERRUPT_HH__ 199