interrupts.hh revision 3827
111244Sandreas.sandberg@arm.com/* 211244Sandreas.sandberg@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 311244Sandreas.sandberg@arm.com * All rights reserved. 411244Sandreas.sandberg@arm.com * 511244Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 611244Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 711244Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 811244Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 911244Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1011244Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1111244Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1211244Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1311244Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1411244Sandreas.sandberg@arm.com * this software without specific prior written permission. 1511260Sandreas.sandberg@arm.com * 1611260Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711260Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811244Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911244Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011244Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111244Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211244Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311244Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411244Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511244Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611244Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711244Sandreas.sandberg@arm.com * 2811244Sandreas.sandberg@arm.com * Authors: Gabe Black 2911244Sandreas.sandberg@arm.com */ 3011244Sandreas.sandberg@arm.com 3111244Sandreas.sandberg@arm.com#ifndef __ARCH_SPARC_INTERRUPT_HH__ 3211244Sandreas.sandberg@arm.com#define __ARCH_SPARC_INTERRUPT_HH__ 3311244Sandreas.sandberg@arm.com 3411244Sandreas.sandberg@arm.com#include "arch/sparc/faults.hh" 3511244Sandreas.sandberg@arm.com#include "cpu/thread_context.hh" 3611244Sandreas.sandberg@arm.com 3711244Sandreas.sandberg@arm.com 3811244Sandreas.sandberg@arm.comnamespace SparcISA 3911244Sandreas.sandberg@arm.com{ 4011244Sandreas.sandberg@arm.com class Interrupts 4111260Sandreas.sandberg@arm.com { 4211260Sandreas.sandberg@arm.com protected: 4311260Sandreas.sandberg@arm.com 4411244Sandreas.sandberg@arm.com 4511244Sandreas.sandberg@arm.com public: 4611244Sandreas.sandberg@arm.com Interrupts() 4711244Sandreas.sandberg@arm.com { 4811244Sandreas.sandberg@arm.com 4911244Sandreas.sandberg@arm.com } 5011260Sandreas.sandberg@arm.com void post(int int_num, int index) 5111260Sandreas.sandberg@arm.com { 5211260Sandreas.sandberg@arm.com 5311260Sandreas.sandberg@arm.com } 5411244Sandreas.sandberg@arm.com 5511244Sandreas.sandberg@arm.com void clear(int int_num, int index) 5611260Sandreas.sandberg@arm.com { 5711244Sandreas.sandberg@arm.com 58 } 59 60 void clear_all() 61 { 62 63 } 64 65 bool check_interrupts(ThreadContext * tc) const 66 { 67 // so far only handle softint interrupts 68 int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); 69 if (int_level) 70 return true; 71 else 72 return false; 73 } 74 75 Fault getInterrupt(ThreadContext * tc) 76 { 77 // conditioning the softint interrups 78 if (tc->readMiscReg(MISCREG_HPSTATE) & hpriv) { 79 // if running in privileged mode, then pend the interrupt 80 return NoFault; 81 } else { 82 int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); 83 if ((int_level <= tc->readMiscReg(MISCREG_PIL)) || 84 !(tc->readMiscReg(MISCREG_PSTATE) & ie)) { 85 // if PIL or no interrupt enabled, then pend the interrupt 86 return NoFault; 87 } else { 88 return new InterruptLevelN(int_level); 89 } 90 } 91 } 92 93 void updateIntrInfo(ThreadContext * tc) 94 { 95 96 } 97 98 void serialize(std::ostream &os) 99 { 100 } 101 102 void unserialize(Checkpoint *cp, const std::string §ion) 103 { 104 } 105 }; 106} 107 108#endif // __ARCH_SPARC_INTERRUPT_HH__ 109