faults.cc revision 8767:e575781f71b8 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "sim/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#if !FULL_SYSTEM
43#include "arch/sparc/process.hh"
44#endif
45#include "mem/page_table.hh"
46#include "sim/process.hh"
47#include "sim/full_system.hh"
48
49using namespace std;
50
51namespace SparcISA
52{
53
54template<> SparcFaultBase::FaultVals
55    SparcFault<PowerOnReset>::vals =
56    {"power_on_reset", 0x001, 0, {H, H, H}};
57
58template<> SparcFaultBase::FaultVals
59    SparcFault<WatchDogReset>::vals =
60    {"watch_dog_reset", 0x002, 120, {H, H, H}};
61
62template<> SparcFaultBase::FaultVals
63    SparcFault<ExternallyInitiatedReset>::vals =
64    {"externally_initiated_reset", 0x003, 110, {H, H, H}};
65
66template<> SparcFaultBase::FaultVals
67    SparcFault<SoftwareInitiatedReset>::vals =
68    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
69
70template<> SparcFaultBase::FaultVals
71    SparcFault<REDStateException>::vals =
72    {"RED_state_exception", 0x005, 1, {H, H, H}};
73
74template<> SparcFaultBase::FaultVals
75    SparcFault<StoreError>::vals =
76    {"store_error", 0x007, 201, {H, H, H}};
77
78template<> SparcFaultBase::FaultVals
79    SparcFault<InstructionAccessException>::vals =
80    {"instruction_access_exception", 0x008, 300, {H, H, H}};
81
82//XXX This trap is apparently dropped from ua2005
83/*template<> SparcFaultBase::FaultVals
84    SparcFault<InstructionAccessMMUMiss>::vals =
85    {"inst_mmu", 0x009, 2, {H, H, H}};*/
86
87template<> SparcFaultBase::FaultVals
88    SparcFault<InstructionAccessError>::vals =
89    {"instruction_access_error", 0x00A, 400, {H, H, H}};
90
91template<> SparcFaultBase::FaultVals
92    SparcFault<IllegalInstruction>::vals =
93    {"illegal_instruction", 0x010, 620, {H, H, H}};
94
95template<> SparcFaultBase::FaultVals
96    SparcFault<PrivilegedOpcode>::vals =
97    {"privileged_opcode", 0x011, 700, {P, SH, SH}};
98
99//XXX This trap is apparently dropped from ua2005
100/*template<> SparcFaultBase::FaultVals
101    SparcFault<UnimplementedLDD>::vals =
102    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
103
104//XXX This trap is apparently dropped from ua2005
105/*template<> SparcFaultBase::FaultVals
106    SparcFault<UnimplementedSTD>::vals =
107    {"unimp_std", 0x013, 6, {H, H, H}};*/
108
109template<> SparcFaultBase::FaultVals
110    SparcFault<FpDisabled>::vals =
111    {"fp_disabled", 0x020, 800, {P, P, H}};
112
113template<> SparcFaultBase::FaultVals
114    SparcFault<FpExceptionIEEE754>::vals =
115    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
116
117template<> SparcFaultBase::FaultVals
118    SparcFault<FpExceptionOther>::vals =
119    {"fp_exception_other", 0x022, 1110, {P, P, H}};
120
121template<> SparcFaultBase::FaultVals
122    SparcFault<TagOverflow>::vals =
123    {"tag_overflow", 0x023, 1400, {P, P, H}};
124
125template<> SparcFaultBase::FaultVals
126    SparcFault<CleanWindow>::vals =
127    {"clean_window", 0x024, 1010, {P, P, H}};
128
129template<> SparcFaultBase::FaultVals
130    SparcFault<DivisionByZero>::vals =
131    {"division_by_zero", 0x028, 1500, {P, P, H}};
132
133template<> SparcFaultBase::FaultVals
134    SparcFault<InternalProcessorError>::vals =
135    {"internal_processor_error", 0x029, 4, {H, H, H}};
136
137template<> SparcFaultBase::FaultVals
138    SparcFault<InstructionInvalidTSBEntry>::vals =
139    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
140
141template<> SparcFaultBase::FaultVals
142    SparcFault<DataInvalidTSBEntry>::vals =
143    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
144
145template<> SparcFaultBase::FaultVals
146    SparcFault<DataAccessException>::vals =
147    {"data_access_exception", 0x030, 1201, {H, H, H}};
148
149//XXX This trap is apparently dropped from ua2005
150/*template<> SparcFaultBase::FaultVals
151    SparcFault<DataAccessMMUMiss>::vals =
152    {"data_mmu", 0x031, 12, {H, H, H}};*/
153
154template<> SparcFaultBase::FaultVals
155    SparcFault<DataAccessError>::vals =
156    {"data_access_error", 0x032, 1210, {H, H, H}};
157
158template<> SparcFaultBase::FaultVals
159    SparcFault<DataAccessProtection>::vals =
160    {"data_access_protection", 0x033, 1207, {H, H, H}};
161
162template<> SparcFaultBase::FaultVals
163    SparcFault<MemAddressNotAligned>::vals =
164    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
165
166template<> SparcFaultBase::FaultVals
167    SparcFault<LDDFMemAddressNotAligned>::vals =
168    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
169
170template<> SparcFaultBase::FaultVals
171    SparcFault<STDFMemAddressNotAligned>::vals =
172    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
173
174template<> SparcFaultBase::FaultVals
175    SparcFault<PrivilegedAction>::vals =
176    {"privileged_action", 0x037, 1110, {H, H, SH}};
177
178template<> SparcFaultBase::FaultVals
179    SparcFault<LDQFMemAddressNotAligned>::vals =
180    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
181
182template<> SparcFaultBase::FaultVals
183    SparcFault<STQFMemAddressNotAligned>::vals =
184    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
185
186template<> SparcFaultBase::FaultVals
187    SparcFault<InstructionRealTranslationMiss>::vals =
188    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
189
190template<> SparcFaultBase::FaultVals
191    SparcFault<DataRealTranslationMiss>::vals =
192    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
193
194//XXX This trap is apparently dropped from ua2005
195/*template<> SparcFaultBase::FaultVals
196    SparcFault<AsyncDataError>::vals =
197    {"async_data", 0x040, 2, {H, H, H}};*/
198
199template<> SparcFaultBase::FaultVals
200    SparcFault<InterruptLevelN>::vals =
201    {"interrupt_level_n", 0x040, 0, {P, P, SH}};
202
203template<> SparcFaultBase::FaultVals
204    SparcFault<HstickMatch>::vals =
205    {"hstick_match", 0x05E, 1601, {H, H, H}};
206
207template<> SparcFaultBase::FaultVals
208    SparcFault<TrapLevelZero>::vals =
209    {"trap_level_zero", 0x05F, 202, {H, H, SH}};
210
211template<> SparcFaultBase::FaultVals
212    SparcFault<InterruptVector>::vals =
213    {"interrupt_vector", 0x060, 2630, {H, H, H}};
214
215template<> SparcFaultBase::FaultVals
216    SparcFault<PAWatchpoint>::vals =
217    {"PA_watchpoint", 0x061, 1209, {H, H, H}};
218
219template<> SparcFaultBase::FaultVals
220    SparcFault<VAWatchpoint>::vals =
221    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
222
223template<> SparcFaultBase::FaultVals
224    SparcFault<FastInstructionAccessMMUMiss>::vals =
225    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
226
227template<> SparcFaultBase::FaultVals
228    SparcFault<FastDataAccessMMUMiss>::vals =
229    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
230
231template<> SparcFaultBase::FaultVals
232    SparcFault<FastDataAccessProtection>::vals =
233    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
234
235template<> SparcFaultBase::FaultVals
236    SparcFault<InstructionBreakpoint>::vals =
237    {"instruction_break", 0x076, 610, {H, H, H}};
238
239template<> SparcFaultBase::FaultVals
240    SparcFault<CpuMondo>::vals =
241    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
242
243template<> SparcFaultBase::FaultVals
244    SparcFault<DevMondo>::vals =
245    {"dev_mondo", 0x07D, 1611, {P, P, SH}};
246
247template<> SparcFaultBase::FaultVals
248    SparcFault<ResumableError>::vals =
249    {"resume_error", 0x07E, 3330, {P, P, SH}};
250
251template<> SparcFaultBase::FaultVals
252    SparcFault<SpillNNormal>::vals =
253    {"spill_n_normal", 0x080, 900, {P, P, H}};
254
255template<> SparcFaultBase::FaultVals
256    SparcFault<SpillNOther>::vals =
257    {"spill_n_other", 0x0A0, 900, {P, P, H}};
258
259template<> SparcFaultBase::FaultVals
260    SparcFault<FillNNormal>::vals =
261    {"fill_n_normal", 0x0C0, 900, {P, P, H}};
262
263template<> SparcFaultBase::FaultVals
264    SparcFault<FillNOther>::vals =
265    {"fill_n_other", 0x0E0, 900, {P, P, H}};
266
267template<> SparcFaultBase::FaultVals
268    SparcFault<TrapInstruction>::vals =
269    {"trap_instruction", 0x100, 1602, {P, P, H}};
270
271/**
272 * This causes the thread context to enter RED state. This causes the side
273 * effects which go with entering RED state because of a trap.
274 */
275
276void
277enterREDState(ThreadContext *tc)
278{
279    //@todo Disable the mmu?
280    //@todo Disable watchpoints?
281    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
282    // HPSTATE.red = 1
283    HPSTATE |= (1 << 5);
284    // HPSTATE.hpriv = 1
285    HPSTATE |= (1 << 2);
286    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
287    // PSTATE.priv is set to 1 here. The manual says it should be 0, but
288    // Legion sets it to 1.
289    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
290    PSTATE |= (1 << 2);
291    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
292}
293
294/**
295 * This sets everything up for a RED state trap except for actually jumping to
296 * the handler.
297 */
298
299void
300doREDFault(ThreadContext *tc, TrapType tt)
301{
302    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
303    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
304    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
305    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
306    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
307    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
308    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
309    MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
310    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
311    PCState pc = tc->pcState();
312
313    TL++;
314
315    Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64);
316
317    // set TSTATE.gl to gl
318    replaceBits(TSTATE, 42, 40, GL);
319    // set TSTATE.ccr to ccr
320    replaceBits(TSTATE, 39, 32, CCR);
321    // set TSTATE.asi to asi
322    replaceBits(TSTATE, 31, 24, ASI);
323    // set TSTATE.pstate to pstate
324    replaceBits(TSTATE, 20, 8, PSTATE);
325    // set TSTATE.cwp to cwp
326    replaceBits(TSTATE, 4, 0, CWP);
327
328    // Write back TSTATE
329    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
330
331    // set TPC to PC
332    tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
333    // set TNPC to NPC
334    tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
335
336    // set HTSTATE.hpstate to hpstate
337    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
338
339    // TT = trap type;
340    tc->setMiscRegNoEffect(MISCREG_TT, tt);
341
342    // Update GL
343    tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
344
345    PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
346    PSTATE |= (1 << 4); // set PSTATE.pef to 1
347    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
348
349    // set HPSTATE.red to 1
350    HPSTATE |= (1 << 5);
351    // set HPSTATE.hpriv to 1
352    HPSTATE |= (1 << 2);
353    // set HPSTATE.ibe to 0
354    HPSTATE &= ~(1 << 10);
355    // set HPSTATE.tlz to 0
356    HPSTATE &= ~(1 << 0);
357    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
358
359    bool changedCWP = true;
360    if (tt == 0x24)
361        CWP++;
362    else if (0x80 <= tt && tt <= 0xbf)
363        CWP += (CANSAVE + 2);
364    else if (0xc0 <= tt && tt <= 0xff)
365        CWP--;
366    else
367        changedCWP = false;
368
369    if (changedCWP) {
370        CWP = (CWP + NWindows) % NWindows;
371        tc->setMiscReg(MISCREG_CWP, CWP);
372    }
373}
374
375/**
376 * This sets everything up for a normal trap except for actually jumping to
377 * the handler.
378 */
379
380void
381doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
382{
383    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
384    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
385    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
386    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
387    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
388    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
389    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
390    MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
391    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
392    PCState pc = tc->pcState();
393
394    // Increment the trap level
395    TL++;
396    tc->setMiscRegNoEffect(MISCREG_TL, TL);
397
398    Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64);
399
400    // Save off state
401
402    // set TSTATE.gl to gl
403    replaceBits(TSTATE, 42, 40, GL);
404    // set TSTATE.ccr to ccr
405    replaceBits(TSTATE, 39, 32, CCR);
406    // set TSTATE.asi to asi
407    replaceBits(TSTATE, 31, 24, ASI);
408    // set TSTATE.pstate to pstate
409    replaceBits(TSTATE, 20, 8, PSTATE);
410    // set TSTATE.cwp to cwp
411    replaceBits(TSTATE, 4, 0, CWP);
412
413    // Write back TSTATE
414    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
415
416    // set TPC to PC
417    tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
418    // set TNPC to NPC
419    tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
420
421    // set HTSTATE.hpstate to hpstate
422    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
423
424    // TT = trap type;
425    tc->setMiscRegNoEffect(MISCREG_TT, tt);
426
427    // Update the global register level
428    if (!gotoHpriv)
429        tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
430    else
431        tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
432
433    // PSTATE.mm is unchanged
434    PSTATE |= (1 << 4); // PSTATE.pef = whether or not an fpu is present
435    PSTATE &= ~(1 << 3); // PSTATE.am = 0
436    PSTATE &= ~(1 << 1); // PSTATE.ie = 0
437    // PSTATE.tle is unchanged
438    // PSTATE.tct = 0
439
440    if (gotoHpriv) {
441        PSTATE &= ~(1 << 9); // PSTATE.cle = 0
442        // The manual says PSTATE.priv should be 0, but Legion leaves it alone
443        HPSTATE &= ~(1 << 5); // HPSTATE.red = 0
444        HPSTATE |= (1 << 2); // HPSTATE.hpriv = 1
445        HPSTATE &= ~(1 << 10); // HPSTATE.ibe = 0
446        // HPSTATE.tlz is unchanged
447        tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
448    } else { // we are going to priv
449        PSTATE |= (1 << 2); // PSTATE.priv = 1
450        replaceBits(PSTATE, 9, 9, PSTATE >> 8); // PSTATE.cle = PSTATE.tle
451    }
452    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
453
454
455    bool changedCWP = true;
456    if (tt == 0x24)
457        CWP++;
458    else if (0x80 <= tt && tt <= 0xbf)
459        CWP += (CANSAVE + 2);
460    else if (0xc0 <= tt && tt <= 0xff)
461        CWP--;
462    else
463        changedCWP = false;
464
465    if (changedCWP) {
466        CWP = (CWP + NWindows) % NWindows;
467        tc->setMiscReg(MISCREG_CWP, CWP);
468    }
469}
470
471void
472getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
473{
474    //XXX The following constant might belong in a header file.
475    const Addr RSTVAddr = 0xFFF0000000ULL;
476    PC = RSTVAddr | ((TT << 5) & 0xFF);
477    NPC = PC + sizeof(MachInst);
478}
479
480void
481getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
482{
483    Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
484    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
485    NPC = PC + sizeof(MachInst);
486}
487
488void
489getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
490{
491    Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
492    PC = (TBA & ~mask(15)) |
493        (TL > 1 ? (1 << 14) : 0) |
494        ((TT << 5) & mask(14));
495    NPC = PC + sizeof(MachInst);
496}
497
498void
499SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
500{
501    FaultBase::invoke(tc);
502    if (!FullSystem)
503        return;
504
505    countStat()++;
506
507    // We can refer to this to see what the trap level -was-, but something
508    // in the middle could change it in the regfile out from under us.
509    MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
510    MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
511    MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
512    MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
513
514    Addr PC, NPC;
515
516    PrivilegeLevel current;
517    if (hpstate & HPSTATE::hpriv)
518        current = Hyperprivileged;
519    else if (pstate & PSTATE::priv)
520        current = Privileged;
521    else
522        current = User;
523
524    PrivilegeLevel level = getNextLevel(current);
525
526    if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
527        getREDVector(5, PC, NPC);
528        doREDFault(tc, tt);
529        // This changes the hpstate and pstate, so we need to make sure we
530        // save the old version on the trap stack in doREDFault.
531        enterREDState(tc);
532    } else if (tl == MaxTL) {
533        panic("Should go to error state here.. crap\n");
534        // Do error_state somehow?
535        // Probably inject a WDR fault using the interrupt mechanism.
536        // What should the PC and NPC be set to?
537    } else if (tl > MaxPTL && level == Privileged) {
538        // guest_watchdog fault
539        doNormalFault(tc, trapType(), true);
540        getHyperVector(tc, PC, NPC, 2);
541    } else if (level == Hyperprivileged ||
542               (level == Privileged && trapType() >= 384)) {
543        doNormalFault(tc, trapType(), true);
544        getHyperVector(tc, PC, NPC, trapType());
545    } else {
546        doNormalFault(tc, trapType(), false);
547        getPrivVector(tc, PC, NPC, trapType(), tl + 1);
548    }
549
550    PCState pc;
551    pc.pc(PC);
552    pc.npc(NPC);
553    pc.nnpc(NPC + sizeof(MachInst));
554    pc.upc(0);
555    pc.nupc(1);
556    tc->pcState(pc);
557}
558
559void
560PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
561{
562    // For SPARC, when a system is first started, there is a power
563    // on reset Trap which sets the processor into the following state.
564    // Bits that aren't set aren't defined on startup.
565
566    tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
567    tc->setMiscRegNoEffect(MISCREG_TT, trapType());
568    tc->setMiscReg(MISCREG_GL, MaxGL);
569
570    // Turn on pef and priv, set everything else to 0
571    tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2));
572
573    // Turn on red and hpriv, set everything else to 0
574    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
575    // HPSTATE.red = 1
576    HPSTATE |= (1 << 5);
577    // HPSTATE.hpriv = 1
578    HPSTATE |= (1 << 2);
579    // HPSTATE.ibe = 0
580    HPSTATE &= ~(1 << 10);
581    // HPSTATE.tlz = 0
582    HPSTATE &= ~(1 << 0);
583    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
584
585    // The tick register is unreadable by nonprivileged software
586    tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
587
588    // Enter RED state. We do this last so that the actual state preserved in
589    // the trap stack is the state from before this fault.
590    enterREDState(tc);
591
592    Addr PC, NPC;
593    getREDVector(trapType(), PC, NPC);
594
595    PCState pc;
596    pc.pc(PC);
597    pc.npc(NPC);
598    pc.nnpc(NPC + sizeof(MachInst));
599    pc.upc(0);
600    pc.nupc(1);
601    tc->pcState(pc);
602
603    // These registers are specified as "undefined" after a POR, and they
604    // should have reasonable values after the miscregfile is reset
605    /*
606    // Clear all the soft interrupt bits
607    softint = 0;
608    // disable timer compare interrupts, reset tick_cmpr
609    tc->setMiscRegNoEffect(MISCREG_
610    tick_cmprFields.int_dis = 1;
611    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
612    stickFields.npt = 1; // The TICK register is unreadable by by !priv
613    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
614    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
615
616    tt[tl] = _trapType;
617
618    hintp = 0; // no interrupts pending
619    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
620    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
621    */
622}
623
624void
625FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
626{
627    if (FullSystem) {
628        SparcFaultBase::invoke(tc, inst);
629    } else {
630        Process *p = tc->getProcessPtr();
631        TlbEntry entry;
632        bool success = p->pTable->lookup(vaddr, entry);
633        if (!success) {
634            panic("Tried to execute unmapped address %#x.\n", vaddr);
635        } else {
636            Addr alignedVaddr = p->pTable->pageAlign(vaddr);
637            tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
638                    p->M5_pid /*context id*/, false, entry.pte);
639        }
640    }
641}
642
643void
644FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
645{
646    if (FullSystem) {
647        SparcFaultBase::invoke(tc, inst);
648    } else {
649        Process *p = tc->getProcessPtr();
650        TlbEntry entry;
651        bool success = p->pTable->lookup(vaddr, entry);
652        if (!success) {
653            if (p->fixupStackFault(vaddr))
654                success = p->pTable->lookup(vaddr, entry);
655        }
656        if (!success) {
657            panic("Tried to access unmapped address %#x.\n", vaddr);
658        } else {
659            Addr alignedVaddr = p->pTable->pageAlign(vaddr);
660            tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
661                    p->M5_pid /*context id*/, false, entry.pte);
662        }
663    }
664}
665
666void
667SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
668{
669#if !FULL_SYSTEM
670    doNormalFault(tc, trapType(), false);
671
672    Process *p = tc->getProcessPtr();
673
674    //XXX This will only work in faults from a SparcLiveProcess
675    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
676    assert(lp);
677
678    // Then adjust the PC and NPC
679    tc->pcState(lp->readSpillStart());
680#else
681    SparcFaultBase::invoke(tc, inst);
682#endif
683}
684
685void
686FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
687{
688#if !FULL_SYSTEM
689    doNormalFault(tc, trapType(), false);
690
691    Process *p = tc->getProcessPtr();
692
693    //XXX This will only work in faults from a SparcLiveProcess
694    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
695    assert(lp);
696
697    // Then adjust the PC and NPC
698    tc->pcState(lp->readFillStart());
699#else
700    SparcFaultBase::invoke(tc, inst);
701#endif
702}
703
704void
705TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
706{
707#if !FULL_SYSTEM
708    // In SE, this mechanism is how the process requests a service from the
709    // operating system. We'll get the process object from the thread context
710    // and let it service the request.
711
712    Process *p = tc->getProcessPtr();
713
714    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
715    assert(lp);
716
717    lp->handleTrap(_n, tc);
718
719    // We need to explicitly advance the pc, since that's not done for us
720    // on a faulting instruction
721    PCState pc = tc->pcState();
722    pc.advance();
723    tc->pcState(pc);
724#else
725    SparcFaultBase::invoke(tc, inst);
726#endif
727}
728
729} // namespace SparcISA
730
731