faults.cc revision 5124 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#if !FULL_SYSTEM
43#include "arch/sparc/process.hh"
44#include "mem/page_table.hh"
45#include "sim/process.hh"
46#endif
47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54    SparcFault<PowerOnReset>::vals =
55    {"power_on_reset", 0x001, 0, {H, H, H}};
56
57template<> SparcFaultBase::FaultVals
58    SparcFault<WatchDogReset>::vals =
59    {"watch_dog_reset", 0x002, 120, {H, H, H}};
60
61template<> SparcFaultBase::FaultVals
62    SparcFault<ExternallyInitiatedReset>::vals =
63    {"externally_initiated_reset", 0x003, 110, {H, H, H}};
64
65template<> SparcFaultBase::FaultVals
66    SparcFault<SoftwareInitiatedReset>::vals =
67    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
68
69template<> SparcFaultBase::FaultVals
70    SparcFault<REDStateException>::vals =
71    {"RED_state_exception", 0x005, 1, {H, H, H}};
72
73template<> SparcFaultBase::FaultVals
74    SparcFault<StoreError>::vals =
75    {"store_error", 0x007, 201, {H, H, H}};
76
77template<> SparcFaultBase::FaultVals
78    SparcFault<InstructionAccessException>::vals =
79    {"instruction_access_exception", 0x008, 300, {H, H, H}};
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83    SparcFault<InstructionAccessMMUMiss>::vals =
84    {"inst_mmu", 0x009, 2, {H, H, H}};*/
85
86template<> SparcFaultBase::FaultVals
87    SparcFault<InstructionAccessError>::vals =
88    {"instruction_access_error", 0x00A, 400, {H, H, H}};
89
90template<> SparcFaultBase::FaultVals
91    SparcFault<IllegalInstruction>::vals =
92    {"illegal_instruction", 0x010, 620, {H, H, H}};
93
94template<> SparcFaultBase::FaultVals
95    SparcFault<PrivilegedOpcode>::vals =
96    {"privileged_opcode", 0x011, 700, {P, SH, SH}};
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100    SparcFault<UnimplementedLDD>::vals =
101    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105    SparcFault<UnimplementedSTD>::vals =
106    {"unimp_std", 0x013, 6, {H, H, H}};*/
107
108template<> SparcFaultBase::FaultVals
109    SparcFault<FpDisabled>::vals =
110    {"fp_disabled", 0x020, 800, {P, P, H}};
111
112template<> SparcFaultBase::FaultVals
113    SparcFault<FpExceptionIEEE754>::vals =
114    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
115
116template<> SparcFaultBase::FaultVals
117    SparcFault<FpExceptionOther>::vals =
118    {"fp_exception_other", 0x022, 1110, {P, P, H}};
119
120template<> SparcFaultBase::FaultVals
121    SparcFault<TagOverflow>::vals =
122    {"tag_overflow", 0x023, 1400, {P, P, H}};
123
124template<> SparcFaultBase::FaultVals
125    SparcFault<CleanWindow>::vals =
126    {"clean_window", 0x024, 1010, {P, P, H}};
127
128template<> SparcFaultBase::FaultVals
129    SparcFault<DivisionByZero>::vals =
130    {"division_by_zero", 0x028, 1500, {P, P, H}};
131
132template<> SparcFaultBase::FaultVals
133    SparcFault<InternalProcessorError>::vals =
134    {"internal_processor_error", 0x029, 4, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
137    SparcFault<InstructionInvalidTSBEntry>::vals =
138    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
139
140template<> SparcFaultBase::FaultVals
141    SparcFault<DataInvalidTSBEntry>::vals =
142    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
143
144template<> SparcFaultBase::FaultVals
145    SparcFault<DataAccessException>::vals =
146    {"data_access_exception", 0x030, 1201, {H, H, H}};
147
148//XXX This trap is apparently dropped from ua2005
149/*template<> SparcFaultBase::FaultVals
150    SparcFault<DataAccessMMUMiss>::vals =
151    {"data_mmu", 0x031, 12, {H, H, H}};*/
152
153template<> SparcFaultBase::FaultVals
154    SparcFault<DataAccessError>::vals =
155    {"data_access_error", 0x032, 1210, {H, H, H}};
156
157template<> SparcFaultBase::FaultVals
158    SparcFault<DataAccessProtection>::vals =
159    {"data_access_protection", 0x033, 1207, {H, H, H}};
160
161template<> SparcFaultBase::FaultVals
162    SparcFault<MemAddressNotAligned>::vals =
163    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
164
165template<> SparcFaultBase::FaultVals
166    SparcFault<LDDFMemAddressNotAligned>::vals =
167    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
168
169template<> SparcFaultBase::FaultVals
170    SparcFault<STDFMemAddressNotAligned>::vals =
171    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
172
173template<> SparcFaultBase::FaultVals
174    SparcFault<PrivilegedAction>::vals =
175    {"privileged_action", 0x037, 1110, {H, H, SH}};
176
177template<> SparcFaultBase::FaultVals
178    SparcFault<LDQFMemAddressNotAligned>::vals =
179    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
180
181template<> SparcFaultBase::FaultVals
182    SparcFault<STQFMemAddressNotAligned>::vals =
183    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
184
185template<> SparcFaultBase::FaultVals
186    SparcFault<InstructionRealTranslationMiss>::vals =
187    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
188
189template<> SparcFaultBase::FaultVals
190    SparcFault<DataRealTranslationMiss>::vals =
191    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
192
193//XXX This trap is apparently dropped from ua2005
194/*template<> SparcFaultBase::FaultVals
195    SparcFault<AsyncDataError>::vals =
196    {"async_data", 0x040, 2, {H, H, H}};*/
197
198template<> SparcFaultBase::FaultVals
199    SparcFault<InterruptLevelN>::vals =
200    {"interrupt_level_n", 0x040, 0, {P, P, SH}};
201
202template<> SparcFaultBase::FaultVals
203    SparcFault<HstickMatch>::vals =
204    {"hstick_match", 0x05E, 1601, {H, H, H}};
205
206template<> SparcFaultBase::FaultVals
207    SparcFault<TrapLevelZero>::vals =
208    {"trap_level_zero", 0x05F, 202, {H, H, SH}};
209
210template<> SparcFaultBase::FaultVals
211    SparcFault<InterruptVector>::vals =
212    {"interrupt_vector", 0x060, 2630, {H, H, H}};
213
214template<> SparcFaultBase::FaultVals
215    SparcFault<PAWatchpoint>::vals =
216    {"PA_watchpoint", 0x061, 1209, {H, H, H}};
217
218template<> SparcFaultBase::FaultVals
219    SparcFault<VAWatchpoint>::vals =
220    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
221
222template<> SparcFaultBase::FaultVals
223    SparcFault<FastInstructionAccessMMUMiss>::vals =
224    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
225
226template<> SparcFaultBase::FaultVals
227    SparcFault<FastDataAccessMMUMiss>::vals =
228    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
229
230template<> SparcFaultBase::FaultVals
231    SparcFault<FastDataAccessProtection>::vals =
232    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
233
234template<> SparcFaultBase::FaultVals
235    SparcFault<InstructionBreakpoint>::vals =
236    {"instruction_break", 0x076, 610, {H, H, H}};
237
238template<> SparcFaultBase::FaultVals
239    SparcFault<CpuMondo>::vals =
240    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
241
242template<> SparcFaultBase::FaultVals
243    SparcFault<DevMondo>::vals =
244    {"dev_mondo", 0x07D, 1611, {P, P, SH}};
245
246template<> SparcFaultBase::FaultVals
247    SparcFault<ResumableError>::vals =
248    {"resume_error", 0x07E, 3330, {P, P, SH}};
249
250template<> SparcFaultBase::FaultVals
251    SparcFault<SpillNNormal>::vals =
252    {"spill_n_normal", 0x080, 900, {P, P, H}};
253
254template<> SparcFaultBase::FaultVals
255    SparcFault<SpillNOther>::vals =
256    {"spill_n_other", 0x0A0, 900, {P, P, H}};
257
258template<> SparcFaultBase::FaultVals
259    SparcFault<FillNNormal>::vals =
260    {"fill_n_normal", 0x0C0, 900, {P, P, H}};
261
262template<> SparcFaultBase::FaultVals
263    SparcFault<FillNOther>::vals =
264    {"fill_n_other", 0x0E0, 900, {P, P, H}};
265
266template<> SparcFaultBase::FaultVals
267    SparcFault<TrapInstruction>::vals =
268    {"trap_instruction", 0x100, 1602, {P, P, H}};
269
270/**
271 * This causes the thread context to enter RED state. This causes the side
272 * effects which go with entering RED state because of a trap.
273 */
274
275void enterREDState(ThreadContext *tc)
276{
277    //@todo Disable the mmu?
278    //@todo Disable watchpoints?
279    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
280    //HPSTATE.red = 1
281    HPSTATE |= (1 << 5);
282    //HPSTATE.hpriv = 1
283    HPSTATE |= (1 << 2);
284    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
285    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
286    //Legion sets it to 1.
287    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
288    PSTATE |= (1 << 2);
289    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
290}
291
292/**
293 * This sets everything up for a RED state trap except for actually jumping to
294 * the handler.
295 */
296
297void doREDFault(ThreadContext *tc, TrapType tt)
298{
299    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
300    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
301    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
302    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
303    //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
304    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
305    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
306    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
307    //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
308    MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
309    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
310    MiscReg PC = tc->readPC();
311    MiscReg NPC = tc->readNextPC();
312
313    TL++;
314
315    if (bits(PSTATE, 3,3)) {
316        PC &= mask(32);
317        NPC &= mask(32);
318    }
319
320    //set TSTATE.gl to gl
321    replaceBits(TSTATE, 42, 40, GL);
322    //set TSTATE.ccr to ccr
323    replaceBits(TSTATE, 39, 32, CCR);
324    //set TSTATE.asi to asi
325    replaceBits(TSTATE, 31, 24, ASI);
326    //set TSTATE.pstate to pstate
327    replaceBits(TSTATE, 20, 8, PSTATE);
328    //set TSTATE.cwp to cwp
329    replaceBits(TSTATE, 4, 0, CWP);
330
331    //Write back TSTATE
332    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
333
334    //set TPC to PC
335    tc->setMiscRegNoEffect(MISCREG_TPC, PC);
336    //set TNPC to NPC
337    tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
338
339    //set HTSTATE.hpstate to hpstate
340    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
341
342    //TT = trap type;
343    tc->setMiscRegNoEffect(MISCREG_TT, tt);
344
345    //Update GL
346    tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
347
348    PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
349    PSTATE |= (1 << 4); //set PSTATE.pef to 1
350    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
351
352    //set HPSTATE.red to 1
353    HPSTATE |= (1 << 5);
354    //set HPSTATE.hpriv to 1
355    HPSTATE |= (1 << 2);
356    //set HPSTATE.ibe to 0
357    HPSTATE &= ~(1 << 10);
358    //set HPSTATE.tlz to 0
359    HPSTATE &= ~(1 << 0);
360    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
361
362    bool changedCWP = true;
363    if(tt == 0x24)
364        CWP++;
365    else if(0x80 <= tt && tt <= 0xbf)
366        CWP += (CANSAVE + 2);
367    else if(0xc0 <= tt && tt <= 0xff)
368        CWP--;
369    else
370        changedCWP = false;
371
372    if(changedCWP)
373    {
374        CWP = (CWP + NWindows) % NWindows;
375        tc->setMiscReg(MISCREG_CWP, CWP);
376    }
377}
378
379/**
380 * This sets everything up for a normal trap except for actually jumping to
381 * the handler.
382 */
383
384void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
385{
386    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
387    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
388    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
389    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
390    //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
391    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
392    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
393    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
394    //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
395    MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
396    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
397    MiscReg PC = tc->readPC();
398    MiscReg NPC = tc->readNextPC();
399
400    if (bits(PSTATE, 3,3)) {
401        PC &= mask(32);
402        NPC &= mask(32);
403    }
404
405    //Increment the trap level
406    TL++;
407    tc->setMiscRegNoEffect(MISCREG_TL, TL);
408
409    //Save off state
410
411    //set TSTATE.gl to gl
412    replaceBits(TSTATE, 42, 40, GL);
413    //set TSTATE.ccr to ccr
414    replaceBits(TSTATE, 39, 32, CCR);
415    //set TSTATE.asi to asi
416    replaceBits(TSTATE, 31, 24, ASI);
417    //set TSTATE.pstate to pstate
418    replaceBits(TSTATE, 20, 8, PSTATE);
419    //set TSTATE.cwp to cwp
420    replaceBits(TSTATE, 4, 0, CWP);
421
422    //Write back TSTATE
423    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
424
425    //set TPC to PC
426    tc->setMiscRegNoEffect(MISCREG_TPC, PC);
427    //set TNPC to NPC
428    tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
429
430    //set HTSTATE.hpstate to hpstate
431    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
432
433    //TT = trap type;
434    tc->setMiscRegNoEffect(MISCREG_TT, tt);
435
436    //Update the global register level
437    if (!gotoHpriv)
438        tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxPGL));
439    else
440        tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
441
442    //PSTATE.mm is unchanged
443    PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
444    PSTATE &= ~(1 << 3); //PSTATE.am = 0
445    PSTATE &= ~(1 << 1); //PSTATE.ie = 0
446    //PSTATE.tle is unchanged
447    //PSTATE.tct = 0
448
449    if (gotoHpriv)
450    {
451        PSTATE &= ~(1 << 9); // PSTATE.cle = 0
452        //The manual says PSTATE.priv should be 0, but Legion leaves it alone
453        HPSTATE &= ~(1 << 5); //HPSTATE.red = 0
454        HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
455        HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
456        //HPSTATE.tlz is unchanged
457        tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
458    } else { // we are going to priv
459        PSTATE |= (1 << 2); //PSTATE.priv = 1
460        replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
461    }
462    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
463
464
465    bool changedCWP = true;
466    if (tt == 0x24)
467        CWP++;
468    else if (0x80 <= tt && tt <= 0xbf)
469        CWP += (CANSAVE + 2);
470    else if (0xc0 <= tt && tt <= 0xff)
471        CWP--;
472    else
473        changedCWP = false;
474
475    if (changedCWP)
476    {
477        CWP = (CWP + NWindows) % NWindows;
478        tc->setMiscReg(MISCREG_CWP, CWP);
479    }
480}
481
482void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
483{
484    //XXX The following constant might belong in a header file.
485    const Addr RSTVAddr = 0xFFF0000000ULL;
486    PC = RSTVAddr | ((TT << 5) & 0xFF);
487    NPC = PC + sizeof(MachInst);
488}
489
490void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
491{
492    Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
493    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
494    NPC = PC + sizeof(MachInst);
495}
496
497void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
498{
499    Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
500    PC = (TBA & ~mask(15)) |
501        (TL > 1 ? (1 << 14) : 0) |
502        ((TT << 5) & mask(14));
503    NPC = PC + sizeof(MachInst);
504}
505
506#if FULL_SYSTEM
507
508void SparcFaultBase::invoke(ThreadContext * tc)
509{
510    //panic("Invoking a second fault!\n");
511    FaultBase::invoke(tc);
512    countStat()++;
513
514    //We can refer to this to see what the trap level -was-, but something
515    //in the middle could change it in the regfile out from under us.
516    MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
517    MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
518    MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
519    MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
520
521    Addr PC, NPC;
522
523    PrivilegeLevel current;
524    if (hpstate & HPSTATE::hpriv)
525        current = Hyperprivileged;
526    else if (pstate & PSTATE::priv)
527        current = Privileged;
528    else
529        current = User;
530
531    PrivilegeLevel level = getNextLevel(current);
532
533    if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
534        getREDVector(5, PC, NPC);
535        doREDFault(tc, tt);
536        //This changes the hpstate and pstate, so we need to make sure we
537        //save the old version on the trap stack in doREDFault.
538        enterREDState(tc);
539    } else if (tl == MaxTL) {
540        panic("Should go to error state here.. crap\n");
541        //Do error_state somehow?
542        //Probably inject a WDR fault using the interrupt mechanism.
543        //What should the PC and NPC be set to?
544    } else if (tl > MaxPTL && level == Privileged) {
545        //guest_watchdog fault
546        doNormalFault(tc, trapType(), true);
547        getHyperVector(tc, PC, NPC, 2);
548    } else if (level == Hyperprivileged ||
549            level == Privileged && trapType() >= 384) {
550        doNormalFault(tc, trapType(), true);
551        getHyperVector(tc, PC, NPC, trapType());
552    } else {
553        doNormalFault(tc, trapType(), false);
554        getPrivVector(tc, PC, NPC, trapType(), tl+1);
555    }
556
557    tc->setPC(PC);
558    tc->setNextPC(NPC);
559    tc->setNextNPC(NPC + sizeof(MachInst));
560}
561
562void PowerOnReset::invoke(ThreadContext * tc)
563{
564    //For SPARC, when a system is first started, there is a power
565    //on reset Trap which sets the processor into the following state.
566    //Bits that aren't set aren't defined on startup.
567
568    tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
569    tc->setMiscRegNoEffect(MISCREG_TT, trapType());
570    tc->setMiscReg(MISCREG_GL, MaxGL);
571
572    //Turn on pef and priv, set everything else to 0
573    tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2));
574
575    //Turn on red and hpriv, set everything else to 0
576    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
577    //HPSTATE.red = 1
578    HPSTATE |= (1 << 5);
579    //HPSTATE.hpriv = 1
580    HPSTATE |= (1 << 2);
581    //HPSTATE.ibe = 0
582    HPSTATE &= ~(1 << 10);
583    //HPSTATE.tlz = 0
584    HPSTATE &= ~(1 << 0);
585    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
586
587    //The tick register is unreadable by nonprivileged software
588    tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
589
590    //Enter RED state. We do this last so that the actual state preserved in
591    //the trap stack is the state from before this fault.
592    enterREDState(tc);
593
594    Addr PC, NPC;
595    getREDVector(trapType(), PC, NPC);
596    tc->setPC(PC);
597    tc->setNextPC(NPC);
598    tc->setNextNPC(NPC + sizeof(MachInst));
599
600    //These registers are specified as "undefined" after a POR, and they
601    //should have reasonable values after the miscregfile is reset
602    /*
603    // Clear all the soft interrupt bits
604    softint = 0;
605    // disable timer compare interrupts, reset tick_cmpr
606    tc->setMiscRegNoEffect(MISCREG_
607    tick_cmprFields.int_dis = 1;
608    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
609    stickFields.npt = 1; //The TICK register is unreadable by by !priv
610    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
611    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
612
613    tt[tl] = _trapType;
614
615    hintp = 0; // no interrupts pending
616    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
617    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
618    */
619}
620
621#else // !FULL_SYSTEM
622
623void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
624{
625    Process *p = tc->getProcessPtr();
626    Addr paddr;
627    bool success = p->pTable->translate(vaddr, paddr);
628    if(!success) {
629        panic("Tried to execute unmapped address %#x.\n", vaddr);
630    } else {
631
632        uint64_t entry = 0;
633        entry |= 0ULL << 1; // Not writable
634        entry |= 0ULL << 2; // Available in nonpriveleged mode
635        entry |= 0ULL << 3; // No side effects
636        entry |= 1ULL << 4; // Virtually cachable
637        entry |= 1ULL << 5; // Physically cachable
638        entry |= 0ULL << 6; // Not locked
639        entry |= mbits(paddr, 39, 13); // Physical address
640        entry |= 0ULL << 48; // size = 8k
641        entry |= 0uLL << 59; // Endianness not inverted
642        entry |= 0ULL << 60; // Not no fault only
643        entry |= 0ULL << 61; // size = 8k
644        entry |= 1ULL << 63; // valid
645        PageTableEntry PTE(entry);
646
647        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
648        tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
649                p->M5_pid /*context id*/, false, PTE);
650    }
651}
652
653void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
654{
655    Process *p = tc->getProcessPtr();
656    Addr paddr;
657    bool success = p->pTable->translate(vaddr, paddr);
658    if(!success) {
659        p->checkAndAllocNextPage(vaddr);
660        success = p->pTable->translate(vaddr, paddr);
661    }
662    if(!success) {
663        panic("Tried to access unmapped address %#x.\n", vaddr);
664    } else {
665
666        uint64_t entry = 0;
667        entry |= 1ULL << 1; // Writable
668        entry |= 0ULL << 2; // Available in nonpriveleged mode
669        entry |= 0ULL << 3; // No side effects
670        entry |= 1ULL << 4; // Virtually cachable
671        entry |= 1ULL << 5; // Physically cachable
672        entry |= 0ULL << 6; // Not locked
673        entry |= mbits(paddr, 39, 13); // Physical address
674        entry |= 0ULL << 48; // size = 8k
675        entry |= 0uLL << 59; // Endianness not inverted
676        entry |= 0ULL << 60; // Not no fault only
677        entry |= 0ULL << 61; // size = 8k
678        entry |= 1ULL << 63; // valid
679        PageTableEntry PTE(entry);
680
681        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
682        tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
683                p->M5_pid /*context id*/, false, PTE);
684    }
685}
686
687void SpillNNormal::invoke(ThreadContext *tc)
688{
689    doNormalFault(tc, trapType(), false);
690
691    Process *p = tc->getProcessPtr();
692
693    //XXX This will only work in faults from a SparcLiveProcess
694    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
695    assert(lp);
696
697    //Then adjust the PC and NPC
698    Addr spillStart = lp->readSpillStart();
699    tc->setPC(spillStart);
700    tc->setNextPC(spillStart + sizeof(MachInst));
701    tc->setNextNPC(spillStart + 2*sizeof(MachInst));
702}
703
704void FillNNormal::invoke(ThreadContext *tc)
705{
706    doNormalFault(tc, trapType(), false);
707
708    Process * p = tc->getProcessPtr();
709
710    //XXX This will only work in faults from a SparcLiveProcess
711    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
712    assert(lp);
713
714    //Then adjust the PC and NPC
715    Addr fillStart = lp->readFillStart();
716    tc->setPC(fillStart);
717    tc->setNextPC(fillStart + sizeof(MachInst));
718    tc->setNextNPC(fillStart + 2*sizeof(MachInst));
719}
720
721void TrapInstruction::invoke(ThreadContext *tc)
722{
723    //In SE, this mechanism is how the process requests a service from the
724    //operating system. We'll get the process object from the thread context
725    //and let it service the request.
726
727    Process *p = tc->getProcessPtr();
728
729    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
730    assert(lp);
731
732    lp->handleTrap(_n, tc);
733
734    //We need to explicitly advance the pc, since that's not done for us
735    //on a faulting instruction
736    tc->setPC(tc->readNextPC());
737    tc->setNextPC(tc->readNextNPC());
738    tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
739}
740
741#endif
742
743} // namespace SparcISA
744
745