faults.cc revision 3928 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#if !FULL_SYSTEM
43#include "arch/sparc/process.hh"
44#include "mem/page_table.hh"
45#include "sim/process.hh"
46#endif
47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54    SparcFault<PowerOnReset>::vals =
55    {"power_on_reset", 0x001, 0, {H, H, H}};
56
57template<> SparcFaultBase::FaultVals
58    SparcFault<WatchDogReset>::vals =
59    {"watch_dog_reset", 0x002, 120, {H, H, H}};
60
61template<> SparcFaultBase::FaultVals
62    SparcFault<ExternallyInitiatedReset>::vals =
63    {"externally_initiated_reset", 0x003, 110, {H, H, H}};
64
65template<> SparcFaultBase::FaultVals
66    SparcFault<SoftwareInitiatedReset>::vals =
67    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
68
69template<> SparcFaultBase::FaultVals
70    SparcFault<REDStateException>::vals =
71    {"RED_state_exception", 0x005, 1, {H, H, H}};
72
73template<> SparcFaultBase::FaultVals
74    SparcFault<StoreError>::vals =
75    {"store_error", 0x007, 201, {H, H, H}};
76
77template<> SparcFaultBase::FaultVals
78    SparcFault<InstructionAccessException>::vals =
79    {"instruction_access_exception", 0x008, 300, {H, H, H}};
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83    SparcFault<InstructionAccessMMUMiss>::vals =
84    {"inst_mmu", 0x009, 2, {H, H, H}};*/
85
86template<> SparcFaultBase::FaultVals
87    SparcFault<InstructionAccessError>::vals =
88    {"instruction_access_error", 0x00A, 400, {H, H, H}};
89
90template<> SparcFaultBase::FaultVals
91    SparcFault<IllegalInstruction>::vals =
92    {"illegal_instruction", 0x010, 620, {H, H, H}};
93
94template<> SparcFaultBase::FaultVals
95    SparcFault<PrivilegedOpcode>::vals =
96    {"privileged_opcode", 0x011, 700, {P, SH, SH}};
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100    SparcFault<UnimplementedLDD>::vals =
101    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105    SparcFault<UnimplementedSTD>::vals =
106    {"unimp_std", 0x013, 6, {H, H, H}};*/
107
108template<> SparcFaultBase::FaultVals
109    SparcFault<FpDisabled>::vals =
110    {"fp_disabled", 0x020, 800, {P, P, H}};
111
112template<> SparcFaultBase::FaultVals
113    SparcFault<FpExceptionIEEE754>::vals =
114    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
115
116template<> SparcFaultBase::FaultVals
117    SparcFault<FpExceptionOther>::vals =
118    {"fp_exception_other", 0x022, 1110, {P, P, H}};
119
120template<> SparcFaultBase::FaultVals
121    SparcFault<TagOverflow>::vals =
122    {"tag_overflow", 0x023, 1400, {P, P, H}};
123
124template<> SparcFaultBase::FaultVals
125    SparcFault<CleanWindow>::vals =
126    {"clean_window", 0x024, 1010, {P, P, H}};
127
128template<> SparcFaultBase::FaultVals
129    SparcFault<DivisionByZero>::vals =
130    {"division_by_zero", 0x028, 1500, {P, P, H}};
131
132template<> SparcFaultBase::FaultVals
133    SparcFault<InternalProcessorError>::vals =
134    {"internal_processor_error", 0x029, 4, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
137    SparcFault<InstructionInvalidTSBEntry>::vals =
138    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
139
140template<> SparcFaultBase::FaultVals
141    SparcFault<DataInvalidTSBEntry>::vals =
142    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
143
144template<> SparcFaultBase::FaultVals
145    SparcFault<DataAccessException>::vals =
146    {"data_access_exception", 0x030, 1201, {H, H, H}};
147
148//XXX This trap is apparently dropped from ua2005
149/*template<> SparcFaultBase::FaultVals
150    SparcFault<DataAccessMMUMiss>::vals =
151    {"data_mmu", 0x031, 12, {H, H, H}};*/
152
153template<> SparcFaultBase::FaultVals
154    SparcFault<DataAccessError>::vals =
155    {"data_access_error", 0x032, 1210, {H, H, H}};
156
157template<> SparcFaultBase::FaultVals
158    SparcFault<DataAccessProtection>::vals =
159    {"data_access_protection", 0x033, 1207, {H, H, H}};
160
161template<> SparcFaultBase::FaultVals
162    SparcFault<MemAddressNotAligned>::vals =
163    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
164
165template<> SparcFaultBase::FaultVals
166    SparcFault<LDDFMemAddressNotAligned>::vals =
167    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
168
169template<> SparcFaultBase::FaultVals
170    SparcFault<STDFMemAddressNotAligned>::vals =
171    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
172
173template<> SparcFaultBase::FaultVals
174    SparcFault<PrivilegedAction>::vals =
175    {"privileged_action", 0x037, 1110, {H, H, SH}};
176
177template<> SparcFaultBase::FaultVals
178    SparcFault<LDQFMemAddressNotAligned>::vals =
179    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
180
181template<> SparcFaultBase::FaultVals
182    SparcFault<STQFMemAddressNotAligned>::vals =
183    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
184
185template<> SparcFaultBase::FaultVals
186    SparcFault<InstructionRealTranslationMiss>::vals =
187    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
188
189template<> SparcFaultBase::FaultVals
190    SparcFault<DataRealTranslationMiss>::vals =
191    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
192
193//XXX This trap is apparently dropped from ua2005
194/*template<> SparcFaultBase::FaultVals
195    SparcFault<AsyncDataError>::vals =
196    {"async_data", 0x040, 2, {H, H, H}};*/
197
198template<> SparcFaultBase::FaultVals
199    SparcFault<InterruptLevelN>::vals =
200    {"interrupt_level_n", 0x040, 0, {P, P, SH}};
201
202template<> SparcFaultBase::FaultVals
203    SparcFault<HstickMatch>::vals =
204    {"hstick_match", 0x05E, 1601, {H, H, H}};
205
206template<> SparcFaultBase::FaultVals
207    SparcFault<TrapLevelZero>::vals =
208    {"trap_level_zero", 0x05F, 202, {H, H, SH}};
209
210template<> SparcFaultBase::FaultVals
211    SparcFault<PAWatchpoint>::vals =
212    {"PA_watchpoint", 0x061, 1209, {H, H, H}};
213
214template<> SparcFaultBase::FaultVals
215    SparcFault<VAWatchpoint>::vals =
216    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
217
218template<> SparcFaultBase::FaultVals
219    SparcFault<FastInstructionAccessMMUMiss>::vals =
220    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
221
222template<> SparcFaultBase::FaultVals
223    SparcFault<FastDataAccessMMUMiss>::vals =
224    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
225
226template<> SparcFaultBase::FaultVals
227    SparcFault<FastDataAccessProtection>::vals =
228    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
229
230template<> SparcFaultBase::FaultVals
231    SparcFault<InstructionBreakpoint>::vals =
232    {"instruction_break", 0x076, 610, {H, H, H}};
233
234template<> SparcFaultBase::FaultVals
235    SparcFault<CpuMondo>::vals =
236    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
237
238template<> SparcFaultBase::FaultVals
239    SparcFault<DevMondo>::vals =
240    {"dev_mondo", 0x07D, 1611, {P, P, SH}};
241
242template<> SparcFaultBase::FaultVals
243    SparcFault<ResumableError>::vals =
244    {"resume_error", 0x07E, 3330, {P, P, SH}};
245
246template<> SparcFaultBase::FaultVals
247    SparcFault<SpillNNormal>::vals =
248    {"spill_n_normal", 0x080, 900, {P, P, H}};
249
250template<> SparcFaultBase::FaultVals
251    SparcFault<SpillNOther>::vals =
252    {"spill_n_other", 0x0A0, 900, {P, P, H}};
253
254template<> SparcFaultBase::FaultVals
255    SparcFault<FillNNormal>::vals =
256    {"fill_n_normal", 0x0C0, 900, {P, P, H}};
257
258template<> SparcFaultBase::FaultVals
259    SparcFault<FillNOther>::vals =
260    {"fill_n_other", 0x0E0, 900, {P, P, H}};
261
262template<> SparcFaultBase::FaultVals
263    SparcFault<TrapInstruction>::vals =
264    {"trap_instruction", 0x100, 1602, {P, P, H}};
265
266#if !FULL_SYSTEM
267template<> SparcFaultBase::FaultVals
268    SparcFault<PageTableFault>::vals =
269    {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
270#endif
271
272/**
273 * This causes the thread context to enter RED state. This causes the side
274 * effects which go with entering RED state because of a trap.
275 */
276
277void enterREDState(ThreadContext *tc)
278{
279    //@todo Disable the mmu?
280    //@todo Disable watchpoints?
281    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
282    //HPSTATE.red = 1
283    HPSTATE |= (1 << 5);
284    //HPSTATE.hpriv = 1
285    HPSTATE |= (1 << 2);
286    tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
287    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
288    //Legion sets it to 1.
289    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
290    PSTATE |= (1 << 2);
291    tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
292}
293
294/**
295 * This sets everything up for a RED state trap except for actually jumping to
296 * the handler.
297 */
298
299void doREDFault(ThreadContext *tc, TrapType tt)
300{
301    MiscReg TL = tc->readMiscReg(MISCREG_TL);
302    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
303    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
304    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
305    MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
306    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
307    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
308    MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
309    MiscReg GL = tc->readMiscReg(MISCREG_GL);
310    MiscReg PC = tc->readPC();
311    MiscReg NPC = tc->readNextPC();
312
313    TL++;
314
315    if (bits(PSTATE, 3,3)) {
316        PC &= mask(32);
317        NPC &= mask(32);
318    }
319
320    //set TSTATE.gl to gl
321    replaceBits(TSTATE, 42, 40, GL);
322    //set TSTATE.ccr to ccr
323    replaceBits(TSTATE, 39, 32, CCR);
324    //set TSTATE.asi to asi
325    replaceBits(TSTATE, 31, 24, ASI);
326    //set TSTATE.pstate to pstate
327    replaceBits(TSTATE, 20, 8, PSTATE);
328    //set TSTATE.cwp to cwp
329    replaceBits(TSTATE, 4, 0, CWP);
330
331    //Write back TSTATE
332    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
333
334    //set TPC to PC
335    tc->setMiscReg(MISCREG_TPC, PC);
336    //set TNPC to NPC
337    tc->setMiscReg(MISCREG_TNPC, NPC);
338
339    //set HTSTATE.hpstate to hpstate
340    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
341
342    //TT = trap type;
343    tc->setMiscReg(MISCREG_TT, tt);
344
345    //Update GL
346    tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
347
348    PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
349    PSTATE |= (1 << 4); //set PSTATE.pef to 1
350    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
351
352    //set HPSTATE.red to 1
353    HPSTATE |= (1 << 5);
354    //set HPSTATE.hpriv to 1
355    HPSTATE |= (1 << 2);
356    //set HPSTATE.ibe to 0
357    HPSTATE &= ~(1 << 10);
358    //set HPSTATE.tlz to 0
359    HPSTATE &= ~(1 << 0);
360    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
361
362    bool changedCWP = true;
363    if(tt == 0x24)
364        CWP++;
365    else if(0x80 <= tt && tt <= 0xbf)
366        CWP += (CANSAVE + 2);
367    else if(0xc0 <= tt && tt <= 0xff)
368        CWP--;
369    else
370        changedCWP = false;
371
372    if(changedCWP)
373    {
374        CWP = (CWP + NWindows) % NWindows;
375        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
376    }
377}
378
379/**
380 * This sets everything up for a normal trap except for actually jumping to
381 * the handler.
382 */
383
384void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
385{
386    MiscReg TL = tc->readMiscReg(MISCREG_TL);
387    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
388    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
389    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
390    MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
391    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
392    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
393    MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
394    MiscReg GL = tc->readMiscReg(MISCREG_GL);
395    MiscReg PC = tc->readPC();
396    MiscReg NPC = tc->readNextPC();
397
398    if (bits(PSTATE, 3,3)) {
399        PC &= mask(32);
400        NPC &= mask(32);
401    }
402
403    //Increment the trap level
404    TL++;
405    tc->setMiscReg(MISCREG_TL, TL);
406
407    //Save off state
408
409    //set TSTATE.gl to gl
410    replaceBits(TSTATE, 42, 40, GL);
411    //set TSTATE.ccr to ccr
412    replaceBits(TSTATE, 39, 32, CCR);
413    //set TSTATE.asi to asi
414    replaceBits(TSTATE, 31, 24, ASI);
415    //set TSTATE.pstate to pstate
416    replaceBits(TSTATE, 20, 8, PSTATE);
417    //set TSTATE.cwp to cwp
418    replaceBits(TSTATE, 4, 0, CWP);
419
420    //Write back TSTATE
421    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
422
423    //set TPC to PC
424    tc->setMiscReg(MISCREG_TPC, PC);
425    //set TNPC to NPC
426    tc->setMiscReg(MISCREG_TNPC, NPC);
427
428    //set HTSTATE.hpstate to hpstate
429    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
430
431    //TT = trap type;
432    tc->setMiscReg(MISCREG_TT, tt);
433
434    //Update the global register level
435    if (!gotoHpriv)
436        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
437    else
438        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
439
440    //PSTATE.mm is unchanged
441    PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
442    PSTATE &= ~(1 << 3); //PSTATE.am = 0
443    PSTATE &= ~(1 << 1); //PSTATE.ie = 0
444    //PSTATE.tle is unchanged
445    //PSTATE.tct = 0
446
447    if (gotoHpriv)
448    {
449        PSTATE &= ~(1 << 9); // PSTATE.cle = 0
450        //The manual says PSTATE.priv should be 0, but Legion leaves it alone
451        HPSTATE &= ~(1 << 5); //HPSTATE.red = 0
452        HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
453        HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
454        //HPSTATE.tlz is unchanged
455        tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
456    } else { // we are going to priv
457        PSTATE |= (1 << 2); //PSTATE.priv = 1
458        replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
459    }
460    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
461
462
463    bool changedCWP = true;
464    if (tt == 0x24)
465        CWP++;
466    else if (0x80 <= tt && tt <= 0xbf)
467        CWP += (CANSAVE + 2);
468    else if (0xc0 <= tt && tt <= 0xff)
469        CWP--;
470    else
471        changedCWP = false;
472
473    if (changedCWP)
474    {
475        CWP = (CWP + NWindows) % NWindows;
476        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
477    }
478}
479
480void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
481{
482    //XXX The following constant might belong in a header file.
483    const Addr RSTVAddr = 0xFFF0000000ULL;
484    PC = RSTVAddr | ((TT << 5) & 0xFF);
485    NPC = PC + sizeof(MachInst);
486}
487
488void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
489{
490    Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
491    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
492    NPC = PC + sizeof(MachInst);
493}
494
495void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
496{
497    Addr TBA = tc->readMiscReg(MISCREG_TBA);
498    PC = (TBA & ~mask(15)) |
499        (TL > 1 ? (1 << 14) : 0) |
500        ((TT << 5) & mask(14));
501    NPC = PC + sizeof(MachInst);
502}
503
504#if FULL_SYSTEM
505
506void SparcFaultBase::invoke(ThreadContext * tc)
507{
508    //panic("Invoking a second fault!\n");
509    FaultBase::invoke(tc);
510    countStat()++;
511
512    //We can refer to this to see what the trap level -was-, but something
513    //in the middle could change it in the regfile out from under us.
514    MiscReg tl = tc->readMiscReg(MISCREG_TL);
515    MiscReg tt = tc->readMiscReg(MISCREG_TT);
516    MiscReg pstate = tc->readMiscReg(MISCREG_PSTATE);
517    MiscReg hpstate = tc->readMiscReg(MISCREG_HPSTATE);
518
519    Addr PC, NPC;
520
521    PrivilegeLevel current;
522    if (hpstate & HPSTATE::hpriv)
523        current = Hyperprivileged;
524    else if (pstate & PSTATE::priv)
525        current = Privileged;
526    else
527        current = User;
528
529    PrivilegeLevel level = getNextLevel(current);
530
531    if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
532        getREDVector(5, PC, NPC);
533        doREDFault(tc, tt);
534        //This changes the hpstate and pstate, so we need to make sure we
535        //save the old version on the trap stack in doREDFault.
536        enterREDState(tc);
537    } else if (tl == MaxTL) {
538        panic("Should go to error state here.. crap\n");
539        //Do error_state somehow?
540        //Probably inject a WDR fault using the interrupt mechanism.
541        //What should the PC and NPC be set to?
542    } else if (tl > MaxPTL && level == Privileged) {
543        //guest_watchdog fault
544        doNormalFault(tc, trapType(), true);
545        getHyperVector(tc, PC, NPC, 2);
546    } else if (level == Hyperprivileged ||
547            level == Privileged && trapType() >= 384) {
548        doNormalFault(tc, trapType(), true);
549        getHyperVector(tc, PC, NPC, trapType());
550    } else {
551        doNormalFault(tc, trapType(), false);
552        getPrivVector(tc, PC, NPC, trapType(), tl+1);
553    }
554
555    tc->setPC(PC);
556    tc->setNextPC(NPC);
557    tc->setNextNPC(NPC + sizeof(MachInst));
558}
559
560void PowerOnReset::invoke(ThreadContext * tc)
561{
562    //For SPARC, when a system is first started, there is a power
563    //on reset Trap which sets the processor into the following state.
564    //Bits that aren't set aren't defined on startup.
565
566    tc->setMiscReg(MISCREG_TL, MaxTL);
567    tc->setMiscReg(MISCREG_TT, trapType());
568    tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
569
570    //Turn on pef and priv, set everything else to 0
571    tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
572
573    //Turn on red and hpriv, set everything else to 0
574    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
575    //HPSTATE.red = 1
576    HPSTATE |= (1 << 5);
577    //HPSTATE.hpriv = 1
578    HPSTATE |= (1 << 2);
579    //HPSTATE.ibe = 0
580    HPSTATE &= ~(1 << 10);
581    //HPSTATE.tlz = 0
582    HPSTATE &= ~(1 << 0);
583    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
584
585    //The tick register is unreadable by nonprivileged software
586    tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
587
588    //Enter RED state. We do this last so that the actual state preserved in
589    //the trap stack is the state from before this fault.
590    enterREDState(tc);
591
592    Addr PC, NPC;
593    getREDVector(trapType(), PC, NPC);
594    tc->setPC(PC);
595    tc->setNextPC(NPC);
596    tc->setNextNPC(NPC + sizeof(MachInst));
597
598    //These registers are specified as "undefined" after a POR, and they
599    //should have reasonable values after the miscregfile is reset
600    /*
601    // Clear all the soft interrupt bits
602    softint = 0;
603    // disable timer compare interrupts, reset tick_cmpr
604    tc->setMiscReg(MISCREG_
605    tick_cmprFields.int_dis = 1;
606    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
607    stickFields.npt = 1; //The TICK register is unreadable by by !priv
608    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
609    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
610
611    tt[tl] = _trapType;
612
613    hintp = 0; // no interrupts pending
614    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
615    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
616    */
617}
618
619#else // !FULL_SYSTEM
620
621void SpillNNormal::invoke(ThreadContext *tc)
622{
623    doNormalFault(tc, trapType(), false);
624
625    Process *p = tc->getProcessPtr();
626
627    //XXX This will only work in faults from a SparcLiveProcess
628    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
629    assert(lp);
630
631    //Then adjust the PC and NPC
632    Addr spillStart = lp->readSpillStart();
633    tc->setPC(spillStart);
634    tc->setNextPC(spillStart + sizeof(MachInst));
635    tc->setNextNPC(spillStart + 2*sizeof(MachInst));
636}
637
638void FillNNormal::invoke(ThreadContext *tc)
639{
640    doNormalFault(tc, trapType(), false);
641
642    Process * p = tc->getProcessPtr();
643
644    //XXX This will only work in faults from a SparcLiveProcess
645    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
646    assert(lp);
647
648    //Then adjust the PC and NPC
649    Addr fillStart = lp->readFillStart();
650    tc->setPC(fillStart);
651    tc->setNextPC(fillStart + sizeof(MachInst));
652    tc->setNextNPC(fillStart + 2*sizeof(MachInst));
653}
654
655void PageTableFault::invoke(ThreadContext *tc)
656{
657    Process *p = tc->getProcessPtr();
658
659    // address is higher than the stack region or in the current stack region
660    if (vaddr > p->stack_base || vaddr > p->stack_min)
661        FaultBase::invoke(tc);
662
663    // We've accessed the next page
664    if (vaddr > p->stack_min - PageBytes) {
665        p->stack_min -= PageBytes;
666        if (p->stack_base - p->stack_min > 8*1024*1024)
667            fatal("Over max stack size for one thread\n");
668        p->pTable->allocate(p->stack_min, PageBytes);
669        warn("Increasing stack size by one page.");
670    } else {
671        FaultBase::invoke(tc);
672    }
673}
674
675#endif
676
677} // namespace SparcISA
678
679