faults.cc revision 3786 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#if !FULL_SYSTEM
43#include "arch/sparc/process.hh"
44#include "mem/page_table.hh"
45#include "sim/process.hh"
46#endif
47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54    SparcFault<PowerOnReset>::vals =
55    {"power_on_reset", 0x001, 0, {H, H, H}};
56
57template<> SparcFaultBase::FaultVals
58    SparcFault<WatchDogReset>::vals =
59    {"watch_dog_reset", 0x002, 120, {H, H, H}};
60
61template<> SparcFaultBase::FaultVals
62    SparcFault<ExternallyInitiatedReset>::vals =
63    {"externally_initiated_reset", 0x003, 110, {H, H, H}};
64
65template<> SparcFaultBase::FaultVals
66    SparcFault<SoftwareInitiatedReset>::vals =
67    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
68
69template<> SparcFaultBase::FaultVals
70    SparcFault<REDStateException>::vals =
71    {"RED_state_exception", 0x005, 1, {H, H, H}};
72
73template<> SparcFaultBase::FaultVals
74    SparcFault<StoreError>::vals =
75    {"store_error", 0x007, 201, {H, H, H}};
76
77template<> SparcFaultBase::FaultVals
78    SparcFault<InstructionAccessException>::vals =
79    {"instruction_access_exception", 0x008, 300, {H, H, H}};
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83    SparcFault<InstructionAccessMMUMiss>::vals =
84    {"inst_mmu", 0x009, 2, {H, H, H}};*/
85
86template<> SparcFaultBase::FaultVals
87    SparcFault<InstructionAccessError>::vals =
88    {"instruction_access_error", 0x00A, 400, {H, H, H}};
89
90template<> SparcFaultBase::FaultVals
91    SparcFault<IllegalInstruction>::vals =
92    {"illegal_instruction", 0x010, 620, {H, H, H}};
93
94template<> SparcFaultBase::FaultVals
95    SparcFault<PrivilegedOpcode>::vals =
96    {"privileged_opcode", 0x011, 700, {P, SH, SH}};
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100    SparcFault<UnimplementedLDD>::vals =
101    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105    SparcFault<UnimplementedSTD>::vals =
106    {"unimp_std", 0x013, 6, {H, H, H}};*/
107
108template<> SparcFaultBase::FaultVals
109    SparcFault<FpDisabled>::vals =
110    {"fp_disabled", 0x020, 800, {P, P, H}};
111
112template<> SparcFaultBase::FaultVals
113    SparcFault<FpExceptionIEEE754>::vals =
114    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
115
116template<> SparcFaultBase::FaultVals
117    SparcFault<FpExceptionOther>::vals =
118    {"fp_exception_other", 0x022, 1110, {P, P, H}};
119
120template<> SparcFaultBase::FaultVals
121    SparcFault<TagOverflow>::vals =
122    {"tag_overflow", 0x023, 1400, {P, P, H}};
123
124template<> SparcFaultBase::FaultVals
125    SparcFault<CleanWindow>::vals =
126    {"clean_window", 0x024, 1010, {P, P, H}};
127
128template<> SparcFaultBase::FaultVals
129    SparcFault<DivisionByZero>::vals =
130    {"division_by_zero", 0x028, 1500, {P, P, H}};
131
132template<> SparcFaultBase::FaultVals
133    SparcFault<InternalProcessorError>::vals =
134    {"internal_processor_error", 0x029, 4, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
137    SparcFault<InstructionInvalidTSBEntry>::vals =
138    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
139
140template<> SparcFaultBase::FaultVals
141    SparcFault<DataInvalidTSBEntry>::vals =
142    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
143
144template<> SparcFaultBase::FaultVals
145    SparcFault<DataAccessException>::vals =
146    {"data_access_exception", 0x030, 1201, {H, H, H}};
147
148//XXX This trap is apparently dropped from ua2005
149/*template<> SparcFaultBase::FaultVals
150    SparcFault<DataAccessMMUMiss>::vals =
151    {"data_mmu", 0x031, 12, {H, H, H}};*/
152
153template<> SparcFaultBase::FaultVals
154    SparcFault<DataAccessError>::vals =
155    {"data_access_error", 0x032, 1210, {H, H, H}};
156
157template<> SparcFaultBase::FaultVals
158    SparcFault<DataAccessProtection>::vals =
159    {"data_access_protection", 0x033, 1207, {H, H, H}};
160
161template<> SparcFaultBase::FaultVals
162    SparcFault<MemAddressNotAligned>::vals =
163    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
164
165template<> SparcFaultBase::FaultVals
166    SparcFault<LDDFMemAddressNotAligned>::vals =
167    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
168
169template<> SparcFaultBase::FaultVals
170    SparcFault<STDFMemAddressNotAligned>::vals =
171    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
172
173template<> SparcFaultBase::FaultVals
174    SparcFault<PrivilegedAction>::vals =
175    {"privileged_action", 0x037, 1110, {H, H, SH}};
176
177template<> SparcFaultBase::FaultVals
178    SparcFault<LDQFMemAddressNotAligned>::vals =
179    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
180
181template<> SparcFaultBase::FaultVals
182    SparcFault<STQFMemAddressNotAligned>::vals =
183    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
184
185template<> SparcFaultBase::FaultVals
186    SparcFault<InstructionRealTranslationMiss>::vals =
187    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
188
189template<> SparcFaultBase::FaultVals
190    SparcFault<DataRealTranslationMiss>::vals =
191    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
192
193//XXX This trap is apparently dropped from ua2005
194/*template<> SparcFaultBase::FaultVals
195    SparcFault<AsyncDataError>::vals =
196    {"async_data", 0x040, 2, {H, H, H}};*/
197
198template<> SparcFaultBase::FaultVals
199    SparcFault<InterruptLevelN>::vals =
200    {"interrupt_level_n", 0x041, 0, {P, P, SH}};
201
202template<> SparcFaultBase::FaultVals
203    SparcFault<HstickMatch>::vals =
204    {"hstick_match", 0x05E, 1601, {H, H, H}};
205
206template<> SparcFaultBase::FaultVals
207    SparcFault<TrapLevelZero>::vals =
208    {"trap_level_zero", 0x05F, 202, {H, H, SH}};
209
210template<> SparcFaultBase::FaultVals
211    SparcFault<PAWatchpoint>::vals =
212    {"PA_watchpoint", 0x061, 1209, {H, H, H}};
213
214template<> SparcFaultBase::FaultVals
215    SparcFault<VAWatchpoint>::vals =
216    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
217
218template<> SparcFaultBase::FaultVals
219    SparcFault<FastInstructionAccessMMUMiss>::vals =
220    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
221
222template<> SparcFaultBase::FaultVals
223    SparcFault<FastDataAccessMMUMiss>::vals =
224    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
225
226template<> SparcFaultBase::FaultVals
227    SparcFault<FastDataAccessProtection>::vals =
228    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
229
230template<> SparcFaultBase::FaultVals
231    SparcFault<InstructionBreakpoint>::vals =
232    {"instruction_break", 0x076, 610, {H, H, H}};
233
234template<> SparcFaultBase::FaultVals
235    SparcFault<CpuMondo>::vals =
236    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
237
238template<> SparcFaultBase::FaultVals
239    SparcFault<DevMondo>::vals =
240    {"dev_mondo", 0x07D, 1611, {P, P, SH}};
241
242template<> SparcFaultBase::FaultVals
243    SparcFault<ResumeableError>::vals =
244    {"resume_error", 0x07E, 3330, {P, P, SH}};
245
246template<> SparcFaultBase::FaultVals
247    SparcFault<SpillNNormal>::vals =
248    {"spill_n_normal", 0x080, 900, {P, P, H}};
249
250template<> SparcFaultBase::FaultVals
251    SparcFault<SpillNOther>::vals =
252    {"spill_n_other", 0x0A0, 900, {P, P, H}};
253
254template<> SparcFaultBase::FaultVals
255    SparcFault<FillNNormal>::vals =
256    {"fill_n_normal", 0x0C0, 900, {P, P, H}};
257
258template<> SparcFaultBase::FaultVals
259    SparcFault<FillNOther>::vals =
260    {"fill_n_other", 0x0E0, 900, {P, P, H}};
261
262template<> SparcFaultBase::FaultVals
263    SparcFault<TrapInstruction>::vals =
264    {"trap_instruction", 0x100, 1602, {P, P, H}};
265
266#if !FULL_SYSTEM
267template<> SparcFaultBase::FaultVals
268    SparcFault<PageTableFault>::vals =
269    {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
270#endif
271
272/**
273 * This causes the thread context to enter RED state. This causes the side
274 * effects which go with entering RED state because of a trap.
275 */
276
277void enterREDState(ThreadContext *tc)
278{
279    //@todo Disable the mmu?
280    //@todo Disable watchpoints?
281    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
282    //HPSTATE.red = 1
283    HPSTATE |= (1 << 5);
284    //HPSTATE.hpriv = 1
285    HPSTATE |= (1 << 2);
286    tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
287    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
288    //Legion sets it to 1.
289    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
290    PSTATE |= (1 << 2);
291    tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
292}
293
294/**
295 * This sets everything up for a RED state trap except for actually jumping to
296 * the handler.
297 */
298
299void doREDFault(ThreadContext *tc, TrapType tt)
300{
301    MiscReg TL = tc->readMiscReg(MISCREG_TL);
302    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
303    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
304    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
305    //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
306    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
307    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
308    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
309    //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
310    MiscReg CANSAVE = tc->readMiscReg(NumIntArchRegs + 3);
311    MiscReg GL = tc->readMiscReg(MISCREG_GL);
312    MiscReg PC = tc->readPC();
313    MiscReg NPC = tc->readNextPC();
314
315    TL++;
316
317    //set TSTATE.gl to gl
318    replaceBits(TSTATE, 42, 40, GL);
319    //set TSTATE.ccr to ccr
320    replaceBits(TSTATE, 39, 32, CCR);
321    //set TSTATE.asi to asi
322    replaceBits(TSTATE, 31, 24, ASI);
323    //set TSTATE.pstate to pstate
324    replaceBits(TSTATE, 20, 8, PSTATE);
325    //set TSTATE.cwp to cwp
326    replaceBits(TSTATE, 4, 0, CWP);
327
328    //Write back TSTATE
329    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
330
331    //set TPC to PC
332    tc->setMiscReg(MISCREG_TPC, PC);
333    //set TNPC to NPC
334    tc->setMiscReg(MISCREG_TNPC, NPC);
335
336    //set HTSTATE.hpstate to hpstate
337    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
338
339    //TT = trap type;
340    tc->setMiscReg(MISCREG_TT, tt);
341
342    //Update GL
343    tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
344
345    //set PSTATE.mm to 00
346    //set PSTATE.pef to 1
347    PSTATE |= (1 << 4);
348    //set PSTATE.am to 0
349    PSTATE &= ~(1 << 3);
350/*    //set PSTATE.priv to 0
351    PSTATE &= ~(1 << 2);*/
352    //set PSTATE.ie to 0
353    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
354    //Legion sets it to 1.
355    PSTATE |= (1 << 2);
356    //set PSTATE.cle to 0
357    PSTATE &= ~(1 << 9);
358    //PSTATE.tle is unchanged
359    //XXX Where is the tct bit?
360    //set PSTATE.tct to 0
361    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
362
363    //set HPSTATE.red to 1
364    HPSTATE |= (1 << 5);
365    //set HPSTATE.hpriv to 1
366    HPSTATE |= (1 << 2);
367    //set HPSTATE.ibe to 0
368    HPSTATE &= ~(1 << 10);
369    //set HPSTATE.tlz to 0
370    HPSTATE &= ~(1 << 0);
371    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
372
373    bool changedCWP = true;
374    if(tt == 0x24)
375        CWP++;
376    else if(0x80 <= tt && tt <= 0xbf)
377        CWP += (CANSAVE + 2);
378    else if(0xc0 <= tt && tt <= 0xff)
379        CWP--;
380    else
381        changedCWP = false;
382
383    if(changedCWP)
384    {
385        CWP = (CWP + NWindows) % NWindows;
386        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
387    }
388}
389
390/**
391 * This sets everything up for a normal trap except for actually jumping to
392 * the handler.
393 */
394
395void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
396{
397    MiscReg TL = tc->readMiscReg(MISCREG_TL);
398    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
399    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
400    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
401    //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
402    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
403    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
404    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
405    //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
406    MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
407    MiscReg GL = tc->readMiscReg(MISCREG_GL);
408    MiscReg PC = tc->readPC();
409    MiscReg NPC = tc->readNextPC();
410
411    //Increment the trap level
412    TL++;
413    tc->setMiscReg(MISCREG_TL, TL);
414
415    //Save off state
416
417    //set TSTATE.gl to gl
418    replaceBits(TSTATE, 42, 40, GL);
419    //set TSTATE.ccr to ccr
420    replaceBits(TSTATE, 39, 32, CCR);
421    //set TSTATE.asi to asi
422    replaceBits(TSTATE, 31, 24, ASI);
423    //set TSTATE.pstate to pstate
424    replaceBits(TSTATE, 20, 8, PSTATE);
425    //set TSTATE.cwp to cwp
426    replaceBits(TSTATE, 4, 0, CWP);
427
428    //Write back TSTATE
429    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
430
431    //set TPC to PC
432    tc->setMiscReg(MISCREG_TPC, PC);
433    //set TNPC to NPC
434    tc->setMiscReg(MISCREG_TNPC, NPC);
435
436    //set HTSTATE.hpstate to hpstate
437    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
438
439    //TT = trap type;
440    tc->setMiscReg(MISCREG_TT, tt);
441
442    //Update the global register level
443    if(!gotoHpriv)
444        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
445    else
446        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
447
448    //PSTATE.mm is unchanged
449    //PSTATE.pef = whether or not an fpu is present
450    //XXX We'll say there's one present, even though there aren't
451    //implementations for a decent number of the instructions
452    PSTATE |= (1 << 4);
453    //PSTATE.am = 0
454    PSTATE &= ~(1 << 3);
455    if(!gotoHpriv)
456    {
457        //PSTATE.priv = 1
458        PSTATE |= (1 << 2);
459        //PSTATE.cle = PSTATE.tle
460        replaceBits(PSTATE, 9, 9, PSTATE >> 8);
461    }
462    else
463    {
464        //PSTATE.priv = 0
465        //PSTATE.priv is set to 1 here. The manual says it should be 0, but
466        //Legion sets it to 1.
467        PSTATE |= (1 << 2);
468        //PSTATE.cle = 0
469        PSTATE &= ~(1 << 9);
470    }
471    //PSTATE.ie = 0
472    PSTATE &= ~(1 << 1);
473    //PSTATE.tle is unchanged
474    //PSTATE.tct = 0
475    //XXX Where exactly is this field?
476    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
477
478    if(gotoHpriv)
479    {
480        //HPSTATE.red = 0
481        HPSTATE &= ~(1 << 5);
482        //HPSTATE.hpriv = 1
483        HPSTATE |= (1 << 2);
484        //HPSTATE.ibe = 0
485        HPSTATE &= ~(1 << 10);
486        //HPSTATE.tlz is unchanged
487        tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
488    }
489
490    bool changedCWP = true;
491    if(tt == 0x24)
492        CWP++;
493    else if(0x80 <= tt && tt <= 0xbf)
494        CWP += (CANSAVE + 2);
495    else if(0xc0 <= tt && tt <= 0xff)
496        CWP--;
497    else
498        changedCWP = false;
499
500    if(changedCWP)
501    {
502        CWP = (CWP + NWindows) % NWindows;
503        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
504    }
505}
506
507void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
508{
509    //XXX The following constant might belong in a header file.
510    const Addr RSTVAddr = 0xFFF0000000ULL;
511    PC = RSTVAddr | ((TT << 5) & 0xFF);
512    NPC = PC + sizeof(MachInst);
513}
514
515void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
516{
517    Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
518    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
519    NPC = PC + sizeof(MachInst);
520}
521
522void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
523{
524    Addr TBA = tc->readMiscReg(MISCREG_TBA);
525    PC = (TBA & ~mask(15)) |
526        (TL > 1 ? (1 << 14) : 0) |
527        ((TT << 5) & mask(14));
528    NPC = PC + sizeof(MachInst);
529}
530
531#if FULL_SYSTEM
532
533void SparcFaultBase::invoke(ThreadContext * tc)
534{
535    panic("Invoking a second fault!\n");
536    FaultBase::invoke(tc);
537    countStat()++;
538
539    //We can refer to this to see what the trap level -was-, but something
540    //in the middle could change it in the regfile out from under us.
541    MiscReg TL = tc->readMiscReg(MISCREG_TL);
542    MiscReg TT = tc->readMiscReg(MISCREG_TT);
543    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
544    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
545
546    Addr PC, NPC;
547
548    PrivilegeLevel current;
549    if(HPSTATE & (1 << 2))
550        current = Hyperprivileged;
551    else if(PSTATE & (1 << 2))
552        current = Privileged;
553    else
554        current = User;
555
556    PrivilegeLevel level = getNextLevel(current);
557
558    if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
559    {
560        getREDVector(5, PC, NPC);
561        doREDFault(tc, TT);
562        //This changes the hpstate and pstate, so we need to make sure we
563        //save the old version on the trap stack in doREDFault.
564        enterREDState(tc);
565    }
566    else if(TL == MaxTL)
567    {
568        //Do error_state somehow?
569        //Probably inject a WDR fault using the interrupt mechanism.
570        //What should the PC and NPC be set to?
571    }
572    else if(TL > MaxPTL && level == Privileged)
573    {
574        //guest_watchdog fault
575        doNormalFault(tc, trapType(), true);
576        getHyperVector(tc, PC, NPC, 2);
577    }
578    else if(level == Hyperprivileged)
579    {
580        doNormalFault(tc, trapType(), true);
581        getHyperVector(tc, PC, NPC, trapType());
582    }
583    else
584    {
585        doNormalFault(tc, trapType(), false);
586        getPrivVector(tc, PC, NPC, trapType(), TL+1);
587    }
588
589    tc->setPC(PC);
590    tc->setNextPC(NPC);
591    tc->setNextNPC(NPC + sizeof(MachInst));
592}
593
594void PowerOnReset::invoke(ThreadContext * tc)
595{
596    //For SPARC, when a system is first started, there is a power
597    //on reset Trap which sets the processor into the following state.
598    //Bits that aren't set aren't defined on startup.
599
600    tc->setMiscReg(MISCREG_TL, MaxTL);
601    tc->setMiscReg(MISCREG_TT, trapType());
602    tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
603
604    //Turn on pef and priv, set everything else to 0
605    tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
606
607    //Turn on red and hpriv, set everything else to 0
608    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
609    //HPSTATE.red = 1
610    HPSTATE |= (1 << 5);
611    //HPSTATE.hpriv = 1
612    HPSTATE |= (1 << 2);
613    //HPSTATE.ibe = 0
614    HPSTATE &= ~(1 << 10);
615    //HPSTATE.tlz = 0
616    HPSTATE &= ~(1 << 0);
617    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
618
619    //The tick register is unreadable by nonprivileged software
620    tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
621
622    //Enter RED state. We do this last so that the actual state preserved in
623    //the trap stack is the state from before this fault.
624    enterREDState(tc);
625
626    Addr PC, NPC;
627    getREDVector(trapType(), PC, NPC);
628    tc->setPC(PC);
629    tc->setNextPC(NPC);
630    tc->setNextNPC(NPC + sizeof(MachInst));
631
632    //These registers are specified as "undefined" after a POR, and they
633    //should have reasonable values after the miscregfile is reset
634    /*
635    // Clear all the soft interrupt bits
636    softint = 0;
637    // disable timer compare interrupts, reset tick_cmpr
638    tc->setMiscReg(MISCREG_
639    tick_cmprFields.int_dis = 1;
640    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
641    stickFields.npt = 1; //The TICK register is unreadable by by !priv
642    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
643    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
644
645    tt[tl] = _trapType;
646
647    hintp = 0; // no interrupts pending
648    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
649    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
650    */
651}
652
653#else // !FULL_SYSTEM
654
655void SpillNNormal::invoke(ThreadContext *tc)
656{
657    doNormalFault(tc, trapType(), false);
658
659    Process *p = tc->getProcessPtr();
660
661    //XXX This will only work in faults from a SparcLiveProcess
662    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
663    assert(lp);
664
665    //Then adjust the PC and NPC
666    Addr spillStart = lp->readSpillStart();
667    tc->setPC(spillStart);
668    tc->setNextPC(spillStart + sizeof(MachInst));
669    tc->setNextNPC(spillStart + 2*sizeof(MachInst));
670}
671
672void FillNNormal::invoke(ThreadContext *tc)
673{
674    doNormalFault(tc, trapType(), false);
675
676    Process * p = tc->getProcessPtr();
677
678    //XXX This will only work in faults from a SparcLiveProcess
679    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
680    assert(lp);
681
682    //Then adjust the PC and NPC
683    Addr fillStart = lp->readFillStart();
684    tc->setPC(fillStart);
685    tc->setNextPC(fillStart + sizeof(MachInst));
686    tc->setNextNPC(fillStart + 2*sizeof(MachInst));
687}
688
689void PageTableFault::invoke(ThreadContext *tc)
690{
691    Process *p = tc->getProcessPtr();
692
693    // We've accessed the next page of the stack, so extend the stack
694    // to cover it.
695    if(vaddr < p->stack_min && vaddr >= p->stack_min - PageBytes)
696    {
697        p->stack_min -= PageBytes;
698        if(p->stack_base - p->stack_min > 8*1024*1024)
699            fatal("Over max stack size for one thread\n");
700        p->pTable->allocate(p->stack_min, PageBytes);
701        warn("Increasing stack size by one page.");
702    }
703    // Otherwise, we have an unexpected page fault. Report that fact,
704    // and what address was accessed to cause the fault.
705    else
706    {
707        panic("Page table fault when accessing virtual address %#x\n", vaddr);
708    }
709}
710
711#endif
712
713} // namespace SparcISA
714
715