faults.cc revision 2800
12221SN/A/* 22221SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32221SN/A * All rights reserved. 42221SN/A * 52221SN/A * Redistribution and use in source and binary forms, with or without 62221SN/A * modification, are permitted provided that the following conditions are 72221SN/A * met: redistributions of source code must retain the above copyright 82221SN/A * notice, this list of conditions and the following disclaimer; 92221SN/A * redistributions in binary form must reproduce the above copyright 102221SN/A * notice, this list of conditions and the following disclaimer in the 112221SN/A * documentation and/or other materials provided with the distribution; 122221SN/A * neither the name of the copyright holders nor the names of its 132221SN/A * contributors may be used to endorse or promote products derived from 142221SN/A * this software without specific prior written permission. 152221SN/A * 162221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182221SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192221SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202221SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232221SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242221SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252221SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262221SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Kevin Lim 302221SN/A */ 312221SN/A 322223SN/A#include "arch/sparc/faults.hh" 332680Sktlim@umich.edu#include "cpu/thread_context.hh" 342221SN/A#include "cpu/base.hh" 352221SN/A#include "base/trace.hh" 362800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 372800Ssaidi@eecs.umich.edu#include "sim/process.hh" 382800Ssaidi@eecs.umich.edu#include "mem/page_table.hh" 392800Ssaidi@eecs.umich.edu#endif 402221SN/A 412223SN/Anamespace SparcISA 422221SN/A{ 432221SN/A 442223SN/AFaultName InternalProcessorError::_name = "intprocerr"; 452223SN/ATrapType InternalProcessorError::_trapType = 0x029; 462223SN/AFaultPriority InternalProcessorError::_priority = 4; 472223SN/AFaultStat InternalProcessorError::_count; 482221SN/A 492223SN/AFaultName MemAddressNotAligned::_name = "unalign"; 502223SN/ATrapType MemAddressNotAligned::_trapType = 0x034; 512223SN/AFaultPriority MemAddressNotAligned::_priority = 10; 522223SN/AFaultStat MemAddressNotAligned::_count; 532221SN/A 542223SN/AFaultName PowerOnReset::_name = "pow_reset"; 552223SN/ATrapType PowerOnReset::_trapType = 0x001; 562223SN/AFaultPriority PowerOnReset::_priority = 0; 572223SN/AFaultStat PowerOnReset::_count; 582221SN/A 592223SN/AFaultName WatchDogReset::_name = "watch_dog_reset"; 602223SN/ATrapType WatchDogReset::_trapType = 0x002; 612223SN/AFaultPriority WatchDogReset::_priority = 1; 622223SN/AFaultStat WatchDogReset::_count; 632221SN/A 642223SN/AFaultName ExternallyInitiatedReset::_name = "extern_reset"; 652223SN/ATrapType ExternallyInitiatedReset::_trapType = 0x003; 662223SN/AFaultPriority ExternallyInitiatedReset::_priority = 1; 672223SN/AFaultStat ExternallyInitiatedReset::_count; 682221SN/A 692223SN/AFaultName SoftwareInitiatedReset::_name = "software_reset"; 702223SN/ATrapType SoftwareInitiatedReset::_trapType = 0x004; 712223SN/AFaultPriority SoftwareInitiatedReset::_priority = 1; 722223SN/AFaultStat SoftwareInitiatedReset::_count; 732221SN/A 742223SN/AFaultName REDStateException::_name = "red_counte"; 752223SN/ATrapType REDStateException::_trapType = 0x005; 762223SN/AFaultPriority REDStateException::_priority = 1; 772223SN/AFaultStat REDStateException::_count; 782221SN/A 792223SN/AFaultName InstructionAccessException::_name = "inst_access"; 802223SN/ATrapType InstructionAccessException::_trapType = 0x008; 812223SN/AFaultPriority InstructionAccessException::_priority = 5; 822223SN/AFaultStat InstructionAccessException::_count; 832221SN/A 842223SN/AFaultName InstructionAccessMMUMiss::_name = "inst_mmu"; 852223SN/ATrapType InstructionAccessMMUMiss::_trapType = 0x009; 862223SN/AFaultPriority InstructionAccessMMUMiss::_priority = 2; 872223SN/AFaultStat InstructionAccessMMUMiss::_count; 882221SN/A 892223SN/AFaultName InstructionAccessError::_name = "inst_error"; 902223SN/ATrapType InstructionAccessError::_trapType = 0x00A; 912223SN/AFaultPriority InstructionAccessError::_priority = 3; 922223SN/AFaultStat InstructionAccessError::_count; 932221SN/A 942223SN/AFaultName IllegalInstruction::_name = "illegal_inst"; 952223SN/ATrapType IllegalInstruction::_trapType = 0x010; 962223SN/AFaultPriority IllegalInstruction::_priority = 7; 972223SN/AFaultStat IllegalInstruction::_count; 982221SN/A 992469SN/AFaultName PrivilegedOpcode::_name = "priv_opcode"; 1002469SN/ATrapType PrivilegedOpcode::_trapType = 0x011; 1012469SN/AFaultPriority PrivilegedOpcode::_priority = 6; 1022469SN/AFaultStat PrivilegedOpcode::_count; 1032221SN/A 1042223SN/AFaultName UnimplementedLDD::_name = "unimp_ldd"; 1052223SN/ATrapType UnimplementedLDD::_trapType = 0x012; 1062223SN/AFaultPriority UnimplementedLDD::_priority = 6; 1072223SN/AFaultStat UnimplementedLDD::_count; 1082221SN/A 1092223SN/AFaultName UnimplementedSTD::_name = "unimp_std"; 1102223SN/ATrapType UnimplementedSTD::_trapType = 0x013; 1112223SN/AFaultPriority UnimplementedSTD::_priority = 6; 1122223SN/AFaultStat UnimplementedSTD::_count; 1132221SN/A 1142223SN/AFaultName FpDisabled::_name = "fp_disabled"; 1152223SN/ATrapType FpDisabled::_trapType = 0x020; 1162223SN/AFaultPriority FpDisabled::_priority = 8; 1172223SN/AFaultStat FpDisabled::_count; 1182221SN/A 1192223SN/AFaultName FpExceptionIEEE754::_name = "fp_754"; 1202223SN/ATrapType FpExceptionIEEE754::_trapType = 0x021; 1212223SN/AFaultPriority FpExceptionIEEE754::_priority = 11; 1222223SN/AFaultStat FpExceptionIEEE754::_count; 1232223SN/A 1242223SN/AFaultName FpExceptionOther::_name = "fp_other"; 1252223SN/ATrapType FpExceptionOther::_trapType = 0x022; 1262223SN/AFaultPriority FpExceptionOther::_priority = 11; 1272223SN/AFaultStat FpExceptionOther::_count; 1282223SN/A 1292223SN/AFaultName TagOverflow::_name = "tag_overflow"; 1302223SN/ATrapType TagOverflow::_trapType = 0x023; 1312223SN/AFaultPriority TagOverflow::_priority = 14; 1322223SN/AFaultStat TagOverflow::_count; 1332223SN/A 1342223SN/AFaultName DivisionByZero::_name = "div_by_zero"; 1352223SN/ATrapType DivisionByZero::_trapType = 0x028; 1362223SN/AFaultPriority DivisionByZero::_priority = 15; 1372223SN/AFaultStat DivisionByZero::_count; 1382223SN/A 1392223SN/AFaultName DataAccessException::_name = "data_access"; 1402223SN/ATrapType DataAccessException::_trapType = 0x030; 1412223SN/AFaultPriority DataAccessException::_priority = 12; 1422223SN/AFaultStat DataAccessException::_count; 1432223SN/A 1442223SN/AFaultName DataAccessMMUMiss::_name = "data_mmu"; 1452223SN/ATrapType DataAccessMMUMiss::_trapType = 0x031; 1462223SN/AFaultPriority DataAccessMMUMiss::_priority = 12; 1472223SN/AFaultStat DataAccessMMUMiss::_count; 1482223SN/A 1492223SN/AFaultName DataAccessError::_name = "data_error"; 1502223SN/ATrapType DataAccessError::_trapType = 0x032; 1512223SN/AFaultPriority DataAccessError::_priority = 12; 1522223SN/AFaultStat DataAccessError::_count; 1532223SN/A 1542223SN/AFaultName DataAccessProtection::_name = "data_protection"; 1552223SN/ATrapType DataAccessProtection::_trapType = 0x033; 1562223SN/AFaultPriority DataAccessProtection::_priority = 12; 1572223SN/AFaultStat DataAccessProtection::_count; 1582223SN/A 1592223SN/AFaultName LDDFMemAddressNotAligned::_name = "unalign_lddf"; 1602223SN/ATrapType LDDFMemAddressNotAligned::_trapType = 0x035; 1612223SN/AFaultPriority LDDFMemAddressNotAligned::_priority = 10; 1622223SN/AFaultStat LDDFMemAddressNotAligned::_count; 1632223SN/A 1642223SN/AFaultName STDFMemAddressNotAligned::_name = "unalign_stdf"; 1652223SN/ATrapType STDFMemAddressNotAligned::_trapType = 0x036; 1662223SN/AFaultPriority STDFMemAddressNotAligned::_priority = 10; 1672223SN/AFaultStat STDFMemAddressNotAligned::_count; 1682223SN/A 1692469SN/AFaultName PrivilegedAction::_name = "priv_action"; 1702469SN/ATrapType PrivilegedAction::_trapType = 0x037; 1712469SN/AFaultPriority PrivilegedAction::_priority = 11; 1722469SN/AFaultStat PrivilegedAction::_count; 1732223SN/A 1742223SN/AFaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf"; 1752223SN/ATrapType LDQFMemAddressNotAligned::_trapType = 0x038; 1762223SN/AFaultPriority LDQFMemAddressNotAligned::_priority = 10; 1772223SN/AFaultStat LDQFMemAddressNotAligned::_count; 1782223SN/A 1792223SN/AFaultName STQFMemAddressNotAligned::_name = "unalign_stqf"; 1802223SN/ATrapType STQFMemAddressNotAligned::_trapType = 0x039; 1812223SN/AFaultPriority STQFMemAddressNotAligned::_priority = 10; 1822223SN/AFaultStat STQFMemAddressNotAligned::_count; 1832223SN/A 1842223SN/AFaultName AsyncDataError::_name = "async_data"; 1852223SN/ATrapType AsyncDataError::_trapType = 0x040; 1862223SN/AFaultPriority AsyncDataError::_priority = 2; 1872223SN/AFaultStat AsyncDataError::_count; 1882223SN/A 1892223SN/AFaultName CleanWindow::_name = "clean_win"; 1902527SN/ATrapType CleanWindow::_trapType = 0x024; 1912223SN/AFaultPriority CleanWindow::_priority = 10; 1922223SN/AFaultStat CleanWindow::_count; 1932223SN/A 1942527SN/A//The enumerated faults 1952527SN/A 1962223SN/AFaultName InterruptLevelN::_name = "interrupt_n"; 1972223SN/ATrapType InterruptLevelN::_baseTrapType = 0x041; 1982223SN/AFaultStat InterruptLevelN::_count; 1992223SN/A 2002223SN/AFaultName SpillNNormal::_name = "spill_n_normal"; 2012223SN/ATrapType SpillNNormal::_baseTrapType = 0x080; 2022223SN/AFaultPriority SpillNNormal::_priority = 9; 2032223SN/AFaultStat SpillNNormal::_count; 2042223SN/A 2052223SN/AFaultName SpillNOther::_name = "spill_n_other"; 2062223SN/ATrapType SpillNOther::_baseTrapType = 0x0A0; 2072223SN/AFaultPriority SpillNOther::_priority = 9; 2082223SN/AFaultStat SpillNOther::_count; 2092223SN/A 2102223SN/AFaultName FillNNormal::_name = "fill_n_normal"; 2112223SN/ATrapType FillNNormal::_baseTrapType = 0x0C0; 2122223SN/AFaultPriority FillNNormal::_priority = 9; 2132223SN/AFaultStat FillNNormal::_count; 2142223SN/A 2152223SN/AFaultName FillNOther::_name = "fill_n_other"; 2162223SN/ATrapType FillNOther::_baseTrapType = 0x0E0; 2172223SN/AFaultPriority FillNOther::_priority = 9; 2182223SN/AFaultStat FillNOther::_count; 2192223SN/A 2202223SN/AFaultName TrapInstruction::_name = "trap_inst_n"; 2212223SN/ATrapType TrapInstruction::_baseTrapType = 0x100; 2222223SN/AFaultPriority TrapInstruction::_priority = 16; 2232223SN/AFaultStat TrapInstruction::_count; 2242223SN/A 2252800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 2262800Ssaidi@eecs.umich.eduFaultName PageTableFault::_name = "page_table_fault"; 2272800Ssaidi@eecs.umich.eduTrapType PageTableFault::_trapType = 0x0000; 2282800Ssaidi@eecs.umich.eduFaultPriority PageTableFault::_priority = 0; 2292800Ssaidi@eecs.umich.eduFaultStat PageTableFault::_count; 2302800Ssaidi@eecs.umich.edu#endif 2312800Ssaidi@eecs.umich.edu 2322221SN/A#if FULL_SYSTEM 2332221SN/A 2342680Sktlim@umich.eduvoid SparcFault::invoke(ThreadContext * tc) 2352221SN/A{ 2362680Sktlim@umich.edu FaultBase::invoke(tc); 2372223SN/A countStat()++; 2382221SN/A 2392223SN/A //Use the SPARC trap state machine 2402223SN/A /*// exception restart address 2412680Sktlim@umich.edu if (setRestartAddress() || !tc->inPalMode()) 2422680Sktlim@umich.edu tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc); 2432221SN/A 2442221SN/A if (skipFaultingInstruction()) { 2452221SN/A // traps... skip faulting instruction. 2462680Sktlim@umich.edu tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, 2472680Sktlim@umich.edu tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); 2482221SN/A } 2492221SN/A 2502680Sktlim@umich.edu if (!tc->inPalMode()) 2512680Sktlim@umich.edu AlphaISA::swap_palshadow(&(tc->regs), true); 2522221SN/A 2532680Sktlim@umich.edu tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); 2542680Sktlim@umich.edu tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/ 2552221SN/A} 2562221SN/A 2572612SN/A#endif 2582612SN/A 2592612SN/A#if !FULL_SYSTEM 2602612SN/A 2612680Sktlim@umich.eduvoid TrapInstruction::invoke(ThreadContext * tc) 2622523SN/A{ 2632719Sktlim@umich.edu // Should be handled in ISA. 2642523SN/A} 2652523SN/A 2662800Ssaidi@eecs.umich.eduvoid PageTableFault::invoke(ThreadContext *tc) 2672800Ssaidi@eecs.umich.edu{ 2682800Ssaidi@eecs.umich.edu Process *p = tc->getProcessPtr(); 2692800Ssaidi@eecs.umich.edu 2702800Ssaidi@eecs.umich.edu // address is higher than the stack region or in the current stack region 2712800Ssaidi@eecs.umich.edu if (vaddr > p->stack_base || vaddr > p->stack_min) 2722800Ssaidi@eecs.umich.edu FaultBase::invoke(tc); 2732800Ssaidi@eecs.umich.edu 2742800Ssaidi@eecs.umich.edu // We've accessed the next page 2752800Ssaidi@eecs.umich.edu if (vaddr > p->stack_min - PageBytes) { 2762800Ssaidi@eecs.umich.edu p->stack_min -= PageBytes; 2772800Ssaidi@eecs.umich.edu if (p->stack_base - p->stack_min > 8*1024*1024) 2782800Ssaidi@eecs.umich.edu fatal("Over max stack size for one thread\n"); 2792800Ssaidi@eecs.umich.edu p->pTable->allocate(p->stack_min, PageBytes); 2802800Ssaidi@eecs.umich.edu warn("Increasing stack size by one page."); 2812800Ssaidi@eecs.umich.edu } else { 2822800Ssaidi@eecs.umich.edu FaultBase::invoke(tc); 2832800Ssaidi@eecs.umich.edu } 2842800Ssaidi@eecs.umich.edu} 2852221SN/A#endif 2862221SN/A 2872223SN/A} // namespace SparcISA 2882221SN/A 289