utility.hh revision 12136:1070125670e2 
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2016-2017 The University of Virginia
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Andreas Hansson
42 *          Sven Karlsson
43 *          Alec Roelke
44 */
45
46#ifndef __ARCH_RISCV_UTILITY_HH__
47#define __ARCH_RISCV_UTILITY_HH__
48
49#include <cmath>
50#include <cstdint>
51#include <sstream>
52#include <string>
53
54#include "arch/riscv/registers.hh"
55#include "base/types.hh"
56#include "cpu/reg_class.hh"
57#include "cpu/static_inst.hh"
58#include "cpu/thread_context.hh"
59
60namespace RiscvISA
61{
62
63template<typename T> inline bool
64isquietnan(T val)
65{
66    return false;
67}
68
69template<> inline bool
70isquietnan<float>(float val)
71{
72    return std::isnan(val)
73        && (reinterpret_cast<uint32_t&>(val)&0x00400000);
74}
75
76template<> inline bool
77isquietnan<double>(double val)
78{
79    return std::isnan(val)
80        && (reinterpret_cast<uint64_t&>(val)&0x0008000000000000ULL);
81}
82
83template<typename T> inline bool
84issignalingnan(T val)
85{
86    return false;
87}
88
89template<> inline bool
90issignalingnan<float>(float val)
91{
92    return std::isnan(val)
93        && (reinterpret_cast<uint32_t&>(val)&0x00200000);
94}
95
96template<> inline bool
97issignalingnan<double>(double val)
98{
99    return std::isnan(val)
100        && (reinterpret_cast<uint64_t&>(val)&0x0004000000000000ULL);
101}
102
103inline PCState
104buildRetPC(const PCState &curPC, const PCState &callPC)
105{
106    PCState retPC = callPC;
107    retPC.advance();
108    retPC.pc(curPC.npc());
109    return retPC;
110}
111
112inline uint64_t
113getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
114{
115    return 0;
116}
117
118inline void startupCPU(ThreadContext *tc, int cpuId)
119{
120}
121
122inline void
123copyRegs(ThreadContext *src, ThreadContext *dest)
124{
125    // First loop through the integer registers.
126    for (int i = 0; i < NumIntRegs; ++i)
127        dest->setIntReg(i, src->readIntReg(i));
128
129    // Lastly copy PC/NPC
130    dest->pcState(src->pcState());
131}
132
133inline std::string
134registerName(RegId reg)
135{
136    if (reg.isIntReg()) {
137        if (reg.index() >= NumIntArchRegs) {
138            /*
139             * This should only happen if a instruction is being speculatively
140             * executed along a not-taken branch, and if that instruction's
141             * width was incorrectly predecoded (i.e., it was predecoded as a
142             * full instruction rather than a compressed one or vice versa).
143             * It also should only happen if a debug flag is on that prints
144             * disassembly information, so rather than panic the incorrect
145             * value is printed for debugging help.
146             */
147            std::stringstream str;
148            str << "?? (x" << reg.index() << ')';
149            return str.str();
150        }
151        return IntRegNames[reg.index()];
152    } else {
153        if (reg.index() >= NumFloatRegs) {
154            std::stringstream str;
155            str << "?? (f" << reg.index() << ')';
156            return str.str();
157        }
158        return FloatRegNames[reg.index()];
159    }
160}
161
162inline void
163skipFunction(ThreadContext *tc)
164{
165    panic("Not Implemented for Riscv");
166}
167
168inline void
169advancePC(PCState &pc, const StaticInstPtr &inst)
170{
171    inst->advancePC(pc);
172}
173
174static inline bool
175inUserMode(ThreadContext *tc)
176{
177    return true;
178}
179
180inline uint64_t
181getExecutingAsid(ThreadContext *tc)
182{
183    return 0;
184}
185
186inline void
187initCPU(ThreadContext *, int cpuId)
188{
189    panic("initCPU not implemented for Riscv.\n");
190}
191
192} // namespace RiscvISA
193
194#endif // __ARCH_RISCV_UTILITY_HH__
195