utility.hh revision 11725:eb58f1bbeac8 
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2016 The University of Virginia
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Andreas Hansson
42 *          Sven Karlsson
43 *          Alec Roelke
44 */
45
46#ifndef __ARCH_RISCV_UTILITY_HH__
47#define __ARCH_RISCV_UTILITY_HH__
48
49#include <cmath>
50#include <cstdint>
51
52#include "base/types.hh"
53#include "cpu/static_inst.hh"
54#include "cpu/thread_context.hh"
55
56namespace RiscvISA
57{
58
59template<typename T> inline bool
60isquietnan(T val)
61{
62    return false;
63}
64
65template<> inline bool
66isquietnan<float>(float val)
67{
68    return std::isnan(val)
69        && (reinterpret_cast<uint32_t&>(val)&0x00400000);
70}
71
72template<> inline bool
73isquietnan<double>(double val)
74{
75    return std::isnan(val)
76        && (reinterpret_cast<uint64_t&>(val)&0x0008000000000000ULL);
77}
78
79template<typename T> inline bool
80issignalingnan(T val)
81{
82    return false;
83}
84
85template<> inline bool
86issignalingnan<float>(float val)
87{
88    return std::isnan(val)
89        && (reinterpret_cast<uint32_t&>(val)&0x00200000);
90}
91
92template<> inline bool
93issignalingnan<double>(double val)
94{
95    return std::isnan(val)
96        && (reinterpret_cast<uint64_t&>(val)&0x0004000000000000ULL);
97}
98
99inline PCState
100buildRetPC(const PCState &curPC, const PCState &callPC)
101{
102    PCState retPC = callPC;
103    retPC.advance();
104    retPC.pc(curPC.npc());
105    return retPC;
106}
107
108inline uint64_t
109getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
110{
111    return 0;
112}
113
114inline void startupCPU(ThreadContext *tc, int cpuId)
115{
116}
117
118inline void
119copyRegs(ThreadContext *src, ThreadContext *dest)
120{
121    // First loop through the integer registers.
122    for (int i = 0; i < NumIntRegs; ++i)
123        dest->setIntReg(i, src->readIntReg(i));
124
125    // Lastly copy PC/NPC
126    dest->pcState(src->pcState());
127}
128
129inline void
130skipFunction(ThreadContext *tc)
131{
132    panic("Not Implemented for Riscv");
133}
134
135inline void
136advancePC(PCState &pc, const StaticInstPtr &inst)
137{
138    inst->advancePC(pc);
139}
140
141static inline bool
142inUserMode(ThreadContext *tc)
143{
144    return true;
145}
146
147inline uint64_t
148getExecutingAsid(ThreadContext *tc)
149{
150    return 0;
151}
152
153inline void
154initCPU(ThreadContext *, int cpuId)
155{
156    panic("initCPU not implemented for Riscv.\n");
157}
158
159} // namespace RiscvISA
160
161#endif // __ARCH_RISCV_UTILITY_HH__
162