tlb.hh revision 11723 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 *          Steve Reinhardt
31 *          Jaidev Patwardhan
32 *          Korey Sewell
33 */
34
35#ifndef __ARCH_RISCV_TLB_HH__
36#define __ARCH_RISCV_TLB_HH__
37
38#include <map>
39
40#include "arch/generic/tlb.hh"
41#include "arch/riscv/isa_traits.hh"
42#include "arch/riscv/pagetable.hh"
43#include "arch/riscv/utility.hh"
44#include "arch/riscv/vtophys.hh"
45#include "base/statistics.hh"
46#include "mem/request.hh"
47#include "params/RiscvTLB.hh"
48#include "sim/sim_object.hh"
49
50class ThreadContext;
51
52/* To maintain compatibility with other architectures, we'll
53   simply create an ITLB and DTLB that will point to the real TLB */
54namespace RiscvISA {
55
56class TLB : public BaseTLB
57{
58  protected:
59    typedef std::multimap<Addr, int> PageTable;
60    PageTable lookupTable;      // Quick lookup into page table
61
62    RiscvISA::PTE *table;        // the Page Table
63    int size;                   // TLB Size
64    int nlu;                    // not last used entry (for replacement)
65
66    void nextnlu() { if (++nlu >= size) nlu = 0; }
67    RiscvISA::PTE *lookup(Addr vpn, uint8_t asn) const;
68
69    mutable Stats::Scalar read_hits;
70    mutable Stats::Scalar read_misses;
71    mutable Stats::Scalar read_acv;
72    mutable Stats::Scalar read_accesses;
73    mutable Stats::Scalar write_hits;
74    mutable Stats::Scalar write_misses;
75    mutable Stats::Scalar write_acv;
76    mutable Stats::Scalar write_accesses;
77    Stats::Formula hits;
78    Stats::Formula misses;
79    Stats::Formula accesses;
80
81  public:
82    typedef RiscvTLBParams Params;
83    TLB(const Params *p);
84
85    int probeEntry(Addr vpn,uint8_t) const;
86    RiscvISA::PTE *getEntry(unsigned) const;
87    virtual ~TLB();
88
89    void takeOverFrom(BaseTLB *otlb) override {}
90
91    int smallPages;
92    int getsize() const { return size; }
93
94    RiscvISA::PTE &index(bool advance = true);
95    void insert(Addr vaddr, RiscvISA::PTE &pte);
96    void insertAt(RiscvISA::PTE &pte, unsigned Index, int _smallPages);
97    void flushAll() override;
98    void demapPage(Addr vaddr, uint64_t asn) override
99    {
100        panic("demapPage unimplemented.\n");
101    }
102
103    // static helper functions... really
104    static bool validVirtualAddress(Addr vaddr);
105
106    static Fault checkCacheability(RequestPtr &req);
107
108    // Checkpointing
109    void serialize(CheckpointOut &cp) const override;
110    void unserialize(CheckpointIn &cp) override;
111
112    void regStats() override;
113
114    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
115    void translateTiming(RequestPtr req, ThreadContext *tc,
116            Translation *translation, Mode mode);
117
118    /** Function stub for CheckerCPU compilation issues. RISC-V does not
119     *  support the Checker model at the moment.
120     */
121    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
122    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
123
124  private:
125    Fault translateInst(RequestPtr req, ThreadContext *tc);
126    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
127};
128
129}
130
131
132
133#endif // __RISCV_MEMORY_HH__
134