registers.hh revision 12850:7036cad54910 
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2016 RISC-V Foundation
16 * Copyright (c) 2016 The University of Virginia
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Andreas Hansson
43 *          Sven Karlsson
44 *          Alec Roelke
45 */
46
47#ifndef __ARCH_RISCV_REGISTERS_HH__
48#define __ARCH_RISCV_REGISTERS_HH__
49
50#include <map>
51#include <string>
52#include <vector>
53
54#include "arch/generic/types.hh"
55#include "arch/generic/vec_reg.hh"
56#include "arch/isa_traits.hh"
57#include "arch/riscv/generated/max_inst_regs.hh"
58#include "base/types.hh"
59
60namespace RiscvISA {
61
62using RiscvISAInst::MaxInstSrcRegs;
63using RiscvISAInst::MaxInstDestRegs;
64const int MaxMiscDestRegs = 1;
65
66typedef uint64_t IntReg;
67typedef uint64_t FloatRegBits;
68typedef double FloatReg;
69typedef uint8_t CCReg; // Not applicable to Riscv
70typedef uint64_t MiscReg;
71
72// dummy typedefs since we don't have vector regs
73const unsigned NumVecElemPerVecReg = 2;
74using VecElem = uint32_t;
75using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
76using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
77using VecRegContainer = VecReg::Container;
78
79const int NumIntArchRegs = 32;
80const int NumMicroIntRegs = 1;
81const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
82const int NumFloatRegs = 32;
83// This has to be one to prevent warnings that are treated as errors
84const unsigned NumVecRegs = 1;
85const int NumCCRegs = 0;
86
87// Semantically meaningful register indices
88const int ZeroReg = 0;
89const int ReturnAddrReg = 1;
90const int StackPointerReg = 2;
91const int GlobalPointerReg = 3;
92const int ThreadPointerReg = 4;
93const int FramePointerReg = 8;
94const int ReturnValueReg = 10;
95const std::vector<int> ReturnValueRegs = {10, 11};
96const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
97const int AMOTempReg = 32;
98
99const int SyscallPseudoReturnReg = 10;
100const std::vector<int> SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
101const int SyscallNumReg = 17;
102
103const std::vector<std::string> IntRegNames = {
104    "zero", "ra", "sp", "gp",
105    "tp", "t0", "t1", "t2",
106    "s0", "s1", "a0", "a1",
107    "a2", "a3", "a4", "a5",
108    "a6", "a7", "s2", "s3",
109    "s4", "s5", "s6", "s7",
110    "s8", "s9", "s10", "s11",
111    "t3", "t4", "t5", "t6"
112};
113const std::vector<std::string> FloatRegNames = {
114    "ft0", "ft1", "ft2", "ft3",
115    "ft4", "ft5", "ft6", "ft7",
116    "fs0", "fs1", "fa0", "fa1",
117    "fa2", "fa3", "fa4", "fa5",
118    "fa6", "fa7", "fs2", "fs3",
119    "fs4", "fs5", "fs6", "fs7",
120    "fs8", "fs9", "fs10", "fs11",
121    "ft8", "ft9", "ft10", "ft11"
122};
123
124enum MiscRegIndex {
125    MISCREG_PRV = 0,
126    MISCREG_ISA,
127    MISCREG_VENDORID,
128    MISCREG_ARCHID,
129    MISCREG_IMPID,
130    MISCREG_HARTID,
131    MISCREG_STATUS,
132    MISCREG_IP,
133    MISCREG_IE,
134    MISCREG_CYCLE,
135    MISCREG_TIME,
136    MISCREG_INSTRET,
137    MISCREG_HPMCOUNTER03,
138    MISCREG_HPMCOUNTER04,
139    MISCREG_HPMCOUNTER05,
140    MISCREG_HPMCOUNTER06,
141    MISCREG_HPMCOUNTER07,
142    MISCREG_HPMCOUNTER08,
143    MISCREG_HPMCOUNTER09,
144    MISCREG_HPMCOUNTER10,
145    MISCREG_HPMCOUNTER11,
146    MISCREG_HPMCOUNTER12,
147    MISCREG_HPMCOUNTER13,
148    MISCREG_HPMCOUNTER14,
149    MISCREG_HPMCOUNTER15,
150    MISCREG_HPMCOUNTER16,
151    MISCREG_HPMCOUNTER17,
152    MISCREG_HPMCOUNTER18,
153    MISCREG_HPMCOUNTER19,
154    MISCREG_HPMCOUNTER20,
155    MISCREG_HPMCOUNTER21,
156    MISCREG_HPMCOUNTER22,
157    MISCREG_HPMCOUNTER23,
158    MISCREG_HPMCOUNTER24,
159    MISCREG_HPMCOUNTER25,
160    MISCREG_HPMCOUNTER26,
161    MISCREG_HPMCOUNTER27,
162    MISCREG_HPMCOUNTER28,
163    MISCREG_HPMCOUNTER29,
164    MISCREG_HPMCOUNTER30,
165    MISCREG_HPMCOUNTER31,
166    MISCREG_HPMEVENT03,
167    MISCREG_HPMEVENT04,
168    MISCREG_HPMEVENT05,
169    MISCREG_HPMEVENT06,
170    MISCREG_HPMEVENT07,
171    MISCREG_HPMEVENT08,
172    MISCREG_HPMEVENT09,
173    MISCREG_HPMEVENT10,
174    MISCREG_HPMEVENT11,
175    MISCREG_HPMEVENT12,
176    MISCREG_HPMEVENT13,
177    MISCREG_HPMEVENT14,
178    MISCREG_HPMEVENT15,
179    MISCREG_HPMEVENT16,
180    MISCREG_HPMEVENT17,
181    MISCREG_HPMEVENT18,
182    MISCREG_HPMEVENT19,
183    MISCREG_HPMEVENT20,
184    MISCREG_HPMEVENT21,
185    MISCREG_HPMEVENT22,
186    MISCREG_HPMEVENT23,
187    MISCREG_HPMEVENT24,
188    MISCREG_HPMEVENT25,
189    MISCREG_HPMEVENT26,
190    MISCREG_HPMEVENT27,
191    MISCREG_HPMEVENT28,
192    MISCREG_HPMEVENT29,
193    MISCREG_HPMEVENT30,
194    MISCREG_HPMEVENT31,
195    MISCREG_TSELECT,
196    MISCREG_TDATA1,
197    MISCREG_TDATA2,
198    MISCREG_TDATA3,
199    MISCREG_DCSR,
200    MISCREG_DPC,
201    MISCREG_DSCRATCH,
202
203    MISCREG_MEDELEG,
204    MISCREG_MIDELEG,
205    MISCREG_MTVEC,
206    MISCREG_MCOUNTEREN,
207    MISCREG_MSCRATCH,
208    MISCREG_MEPC,
209    MISCREG_MCAUSE,
210    MISCREG_MTVAL,
211    MISCREG_PMPCFG0,
212    // pmpcfg1 rv32 only
213    MISCREG_PMPCFG2,
214    // pmpcfg3 rv32 only
215    MISCREG_PMPADDR00,
216    MISCREG_PMPADDR01,
217    MISCREG_PMPADDR02,
218    MISCREG_PMPADDR03,
219    MISCREG_PMPADDR04,
220    MISCREG_PMPADDR05,
221    MISCREG_PMPADDR06,
222    MISCREG_PMPADDR07,
223    MISCREG_PMPADDR08,
224    MISCREG_PMPADDR09,
225    MISCREG_PMPADDR10,
226    MISCREG_PMPADDR11,
227    MISCREG_PMPADDR12,
228    MISCREG_PMPADDR13,
229    MISCREG_PMPADDR14,
230    MISCREG_PMPADDR15,
231
232    MISCREG_SEDELEG,
233    MISCREG_SIDELEG,
234    MISCREG_STVEC,
235    MISCREG_SCOUNTEREN,
236    MISCREG_SSCRATCH,
237    MISCREG_SEPC,
238    MISCREG_SCAUSE,
239    MISCREG_STVAL,
240    MISCREG_SATP,
241
242    MISCREG_UTVEC,
243    MISCREG_USCRATCH,
244    MISCREG_UEPC,
245    MISCREG_UCAUSE,
246    MISCREG_UTVAL,
247    MISCREG_FFLAGS,
248    MISCREG_FRM,
249
250    NUM_MISCREGS
251};
252const int NumMiscRegs = NUM_MISCREGS;
253
254enum CSRIndex {
255    CSR_USTATUS = 0x000,
256    CSR_UIE = 0x004,
257    CSR_UTVEC = 0x005,
258    CSR_USCRATCH = 0x040,
259    CSR_UEPC = 0x041,
260    CSR_UCAUSE = 0x042,
261    CSR_UTVAL = 0x043,
262    CSR_UIP = 0x044,
263    CSR_FFLAGS = 0x001,
264    CSR_FRM = 0x002,
265    CSR_FCSR = 0x003,
266    CSR_CYCLE = 0xC00,
267    CSR_TIME = 0xC01,
268    CSR_INSTRET = 0xC02,
269    CSR_HPMCOUNTER03 = 0xC03,
270    CSR_HPMCOUNTER04 = 0xC04,
271    CSR_HPMCOUNTER05 = 0xC05,
272    CSR_HPMCOUNTER06 = 0xC06,
273    CSR_HPMCOUNTER07 = 0xC07,
274    CSR_HPMCOUNTER08 = 0xC08,
275    CSR_HPMCOUNTER09 = 0xC09,
276    CSR_HPMCOUNTER10 = 0xC0A,
277    CSR_HPMCOUNTER11 = 0xC0B,
278    CSR_HPMCOUNTER12 = 0xC0C,
279    CSR_HPMCOUNTER13 = 0xC0D,
280    CSR_HPMCOUNTER14 = 0xC0E,
281    CSR_HPMCOUNTER15 = 0xC0F,
282    CSR_HPMCOUNTER16 = 0xC10,
283    CSR_HPMCOUNTER17 = 0xC11,
284    CSR_HPMCOUNTER18 = 0xC12,
285    CSR_HPMCOUNTER19 = 0xC13,
286    CSR_HPMCOUNTER20 = 0xC14,
287    CSR_HPMCOUNTER21 = 0xC15,
288    CSR_HPMCOUNTER22 = 0xC16,
289    CSR_HPMCOUNTER23 = 0xC17,
290    CSR_HPMCOUNTER24 = 0xC18,
291    CSR_HPMCOUNTER25 = 0xC19,
292    CSR_HPMCOUNTER26 = 0xC1A,
293    CSR_HPMCOUNTER27 = 0xC1B,
294    CSR_HPMCOUNTER28 = 0xC1C,
295    CSR_HPMCOUNTER29 = 0xC1D,
296    CSR_HPMCOUNTER30 = 0xC1E,
297    CSR_HPMCOUNTER31 = 0xC1F,
298    // HPMCOUNTERH rv32 only
299
300    CSR_SSTATUS = 0x100,
301    CSR_SEDELEG = 0x102,
302    CSR_SIDELEG = 0x103,
303    CSR_SIE = 0x104,
304    CSR_STVEC = 0x105,
305    CSR_SSCRATCH = 0x140,
306    CSR_SEPC = 0x141,
307    CSR_SCAUSE = 0x142,
308    CSR_STVAL = 0x143,
309    CSR_SIP = 0x144,
310    CSR_SATP = 0x180,
311
312    CSR_MVENDORID = 0xF11,
313    CSR_MARCHID = 0xF12,
314    CSR_MIMPID = 0xF13,
315    CSR_MHARTID = 0xF14,
316    CSR_MSTATUS = 0x300,
317    CSR_MISA = 0x301,
318    CSR_MEDELEG = 0x302,
319    CSR_MIDELEG = 0x303,
320    CSR_MIE = 0x304,
321    CSR_MTVEC = 0x305,
322    CSR_MSCRATCH = 0x340,
323    CSR_MEPC = 0x341,
324    CSR_MCAUSE = 0x342,
325    CSR_MTVAL = 0x343,
326    CSR_MIP = 0x344,
327    CSR_PMPCFG0 = 0x3A0,
328    // pmpcfg1 rv32 only
329    CSR_PMPCFG2 = 0x3A2,
330    // pmpcfg3 rv32 only
331    CSR_PMPADDR00 = 0x3B0,
332    CSR_PMPADDR01 = 0x3B1,
333    CSR_PMPADDR02 = 0x3B2,
334    CSR_PMPADDR03 = 0x3B3,
335    CSR_PMPADDR04 = 0x3B4,
336    CSR_PMPADDR05 = 0x3B5,
337    CSR_PMPADDR06 = 0x3B6,
338    CSR_PMPADDR07 = 0x3B7,
339    CSR_PMPADDR08 = 0x3B8,
340    CSR_PMPADDR09 = 0x3B9,
341    CSR_PMPADDR10 = 0x3BA,
342    CSR_PMPADDR11 = 0x3BB,
343    CSR_PMPADDR12 = 0x3BC,
344    CSR_PMPADDR13 = 0x3BD,
345    CSR_PMPADDR14 = 0x3BE,
346    CSR_PMPADDR15 = 0x3BF,
347    CSR_MCYCLE = 0xB00,
348    CSR_MINSTRET = 0xB02,
349    CSR_MHPMCOUNTER03 = 0xC03,
350    CSR_MHPMCOUNTER04 = 0xC04,
351    CSR_MHPMCOUNTER05 = 0xC05,
352    CSR_MHPMCOUNTER06 = 0xC06,
353    CSR_MHPMCOUNTER07 = 0xC07,
354    CSR_MHPMCOUNTER08 = 0xC08,
355    CSR_MHPMCOUNTER09 = 0xC09,
356    CSR_MHPMCOUNTER10 = 0xC0A,
357    CSR_MHPMCOUNTER11 = 0xC0B,
358    CSR_MHPMCOUNTER12 = 0xC0C,
359    CSR_MHPMCOUNTER13 = 0xC0D,
360    CSR_MHPMCOUNTER14 = 0xC0E,
361    CSR_MHPMCOUNTER15 = 0xC0F,
362    CSR_MHPMCOUNTER16 = 0xC10,
363    CSR_MHPMCOUNTER17 = 0xC11,
364    CSR_MHPMCOUNTER18 = 0xC12,
365    CSR_MHPMCOUNTER19 = 0xC13,
366    CSR_MHPMCOUNTER20 = 0xC14,
367    CSR_MHPMCOUNTER21 = 0xC15,
368    CSR_MHPMCOUNTER22 = 0xC16,
369    CSR_MHPMCOUNTER23 = 0xC17,
370    CSR_MHPMCOUNTER24 = 0xC18,
371    CSR_MHPMCOUNTER25 = 0xC19,
372    CSR_MHPMCOUNTER26 = 0xC1A,
373    CSR_MHPMCOUNTER27 = 0xC1B,
374    CSR_MHPMCOUNTER28 = 0xC1C,
375    CSR_MHPMCOUNTER29 = 0xC1D,
376    CSR_MHPMCOUNTER30 = 0xC1E,
377    CSR_MHPMCOUNTER31 = 0xC1F,
378    // MHPMCOUNTERH rv32 only
379    CSR_MHPMEVENT03 = 0x323,
380    CSR_MHPMEVENT04 = 0x324,
381    CSR_MHPMEVENT05 = 0x325,
382    CSR_MHPMEVENT06 = 0x326,
383    CSR_MHPMEVENT07 = 0x327,
384    CSR_MHPMEVENT08 = 0x328,
385    CSR_MHPMEVENT09 = 0x329,
386    CSR_MHPMEVENT10 = 0x32A,
387    CSR_MHPMEVENT11 = 0x32B,
388    CSR_MHPMEVENT12 = 0x32C,
389    CSR_MHPMEVENT13 = 0x32D,
390    CSR_MHPMEVENT14 = 0x32E,
391    CSR_MHPMEVENT15 = 0x32F,
392    CSR_MHPMEVENT16 = 0x330,
393    CSR_MHPMEVENT17 = 0x331,
394    CSR_MHPMEVENT18 = 0x332,
395    CSR_MHPMEVENT19 = 0x333,
396    CSR_MHPMEVENT20 = 0x334,
397    CSR_MHPMEVENT21 = 0x335,
398    CSR_MHPMEVENT22 = 0x336,
399    CSR_MHPMEVENT23 = 0x337,
400    CSR_MHPMEVENT24 = 0x338,
401    CSR_MHPMEVENT25 = 0x339,
402    CSR_MHPMEVENT26 = 0x33A,
403    CSR_MHPMEVENT27 = 0x33B,
404    CSR_MHPMEVENT28 = 0x33C,
405    CSR_MHPMEVENT29 = 0x33D,
406    CSR_MHPMEVENT30 = 0x33E,
407    CSR_MHPMEVENT31 = 0x33F,
408
409    CSR_TSELECT = 0x7A0,
410    CSR_TDATA1 = 0x7A1,
411    CSR_TDATA2 = 0x7A2,
412    CSR_TDATA3 = 0x7A3,
413    CSR_DCSR = 0x7B0,
414    CSR_DPC = 0x7B1,
415    CSR_DSCRATCH = 0x7B2
416};
417
418struct CSRMetadata
419{
420    const std::string name;
421    const int physIndex;
422};
423
424const std::map<int, CSRMetadata> CSRData = {
425    {CSR_USTATUS, {"ustatus", MISCREG_STATUS}},
426    {CSR_UIE, {"uie", MISCREG_IE}},
427    {CSR_UTVEC, {"utvec", MISCREG_UTVEC}},
428    {CSR_USCRATCH, {"uscratch", MISCREG_USCRATCH}},
429    {CSR_UEPC, {"uepc", MISCREG_UEPC}},
430    {CSR_UCAUSE, {"ucause", MISCREG_UCAUSE}},
431    {CSR_UTVAL, {"utval", MISCREG_UTVAL}},
432    {CSR_UIP, {"uip", MISCREG_IP}},
433    {CSR_FFLAGS, {"fflags", MISCREG_FFLAGS}},
434    {CSR_FRM, {"frm", MISCREG_FRM}},
435    {CSR_FCSR, {"fcsr", MISCREG_FFLAGS}}, // Actually FRM << 5 | FFLAGS
436    {CSR_CYCLE, {"cycle", MISCREG_CYCLE}},
437    {CSR_TIME, {"time", MISCREG_TIME}},
438    {CSR_INSTRET, {"instret", MISCREG_INSTRET}},
439    {CSR_HPMCOUNTER03, {"hpmcounter03", MISCREG_HPMCOUNTER03}},
440    {CSR_HPMCOUNTER04, {"hpmcounter04", MISCREG_HPMCOUNTER04}},
441    {CSR_HPMCOUNTER05, {"hpmcounter05", MISCREG_HPMCOUNTER05}},
442    {CSR_HPMCOUNTER06, {"hpmcounter06", MISCREG_HPMCOUNTER06}},
443    {CSR_HPMCOUNTER07, {"hpmcounter07", MISCREG_HPMCOUNTER07}},
444    {CSR_HPMCOUNTER08, {"hpmcounter08", MISCREG_HPMCOUNTER08}},
445    {CSR_HPMCOUNTER09, {"hpmcounter09", MISCREG_HPMCOUNTER09}},
446    {CSR_HPMCOUNTER10, {"hpmcounter10", MISCREG_HPMCOUNTER10}},
447    {CSR_HPMCOUNTER11, {"hpmcounter11", MISCREG_HPMCOUNTER11}},
448    {CSR_HPMCOUNTER12, {"hpmcounter12", MISCREG_HPMCOUNTER12}},
449    {CSR_HPMCOUNTER13, {"hpmcounter13", MISCREG_HPMCOUNTER13}},
450    {CSR_HPMCOUNTER14, {"hpmcounter14", MISCREG_HPMCOUNTER14}},
451    {CSR_HPMCOUNTER15, {"hpmcounter15", MISCREG_HPMCOUNTER15}},
452    {CSR_HPMCOUNTER16, {"hpmcounter16", MISCREG_HPMCOUNTER16}},
453    {CSR_HPMCOUNTER17, {"hpmcounter17", MISCREG_HPMCOUNTER17}},
454    {CSR_HPMCOUNTER18, {"hpmcounter18", MISCREG_HPMCOUNTER18}},
455    {CSR_HPMCOUNTER19, {"hpmcounter19", MISCREG_HPMCOUNTER19}},
456    {CSR_HPMCOUNTER20, {"hpmcounter20", MISCREG_HPMCOUNTER20}},
457    {CSR_HPMCOUNTER21, {"hpmcounter21", MISCREG_HPMCOUNTER21}},
458    {CSR_HPMCOUNTER22, {"hpmcounter22", MISCREG_HPMCOUNTER22}},
459    {CSR_HPMCOUNTER23, {"hpmcounter23", MISCREG_HPMCOUNTER23}},
460    {CSR_HPMCOUNTER24, {"hpmcounter24", MISCREG_HPMCOUNTER24}},
461    {CSR_HPMCOUNTER25, {"hpmcounter25", MISCREG_HPMCOUNTER25}},
462    {CSR_HPMCOUNTER26, {"hpmcounter26", MISCREG_HPMCOUNTER26}},
463    {CSR_HPMCOUNTER27, {"hpmcounter27", MISCREG_HPMCOUNTER27}},
464    {CSR_HPMCOUNTER28, {"hpmcounter28", MISCREG_HPMCOUNTER28}},
465    {CSR_HPMCOUNTER29, {"hpmcounter29", MISCREG_HPMCOUNTER29}},
466    {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}},
467    {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}},
468
469    {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
470    {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}},
471    {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}},
472    {CSR_SIE, {"sie", MISCREG_IE}},
473    {CSR_STVEC, {"stvec", MISCREG_STVEC}},
474    {CSR_SSCRATCH, {"sscratch", MISCREG_SSCRATCH}},
475    {CSR_SEPC, {"sepc", MISCREG_SEPC}},
476    {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}},
477    {CSR_STVAL, {"stval", MISCREG_STVAL}},
478    {CSR_SIP, {"sip", MISCREG_IP}},
479    {CSR_SATP, {"satp", MISCREG_SATP}},
480
481    {CSR_MVENDORID, {"mvendorid", MISCREG_VENDORID}},
482    {CSR_MARCHID, {"marchid", MISCREG_ARCHID}},
483    {CSR_MIMPID, {"mimpid", MISCREG_IMPID}},
484    {CSR_MHARTID, {"mhartid", MISCREG_HARTID}},
485    {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
486    {CSR_MISA, {"misa", MISCREG_ISA}},
487    {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}},
488    {CSR_MIDELEG, {"mideleg", MISCREG_MIDELEG}},
489    {CSR_MIE, {"mie", MISCREG_IE}},
490    {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}},
491    {CSR_MSCRATCH, {"mscratch", MISCREG_MSCRATCH}},
492    {CSR_MEPC, {"mepc", MISCREG_MEPC}},
493    {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}},
494    {CSR_MTVAL, {"mtval", MISCREG_MTVAL}},
495    {CSR_MIP, {"mip", MISCREG_IP}},
496    {CSR_PMPCFG0, {"pmpcfg0", MISCREG_PMPCFG0}},
497    // pmpcfg1 rv32 only
498    {CSR_PMPCFG2, {"pmpcfg2", MISCREG_PMPCFG2}},
499    // pmpcfg3 rv32 only
500    {CSR_PMPADDR00, {"pmpaddr0", MISCREG_PMPADDR00}},
501    {CSR_PMPADDR01, {"pmpaddr1", MISCREG_PMPADDR01}},
502    {CSR_PMPADDR02, {"pmpaddr2", MISCREG_PMPADDR02}},
503    {CSR_PMPADDR03, {"pmpaddr3", MISCREG_PMPADDR03}},
504    {CSR_PMPADDR04, {"pmpaddr4", MISCREG_PMPADDR04}},
505    {CSR_PMPADDR05, {"pmpaddr5", MISCREG_PMPADDR05}},
506    {CSR_PMPADDR06, {"pmpaddr6", MISCREG_PMPADDR06}},
507    {CSR_PMPADDR07, {"pmpaddr7", MISCREG_PMPADDR07}},
508    {CSR_PMPADDR08, {"pmpaddr8", MISCREG_PMPADDR08}},
509    {CSR_PMPADDR09, {"pmpaddr9", MISCREG_PMPADDR09}},
510    {CSR_PMPADDR10, {"pmpaddr10", MISCREG_PMPADDR10}},
511    {CSR_PMPADDR11, {"pmpaddr11", MISCREG_PMPADDR11}},
512    {CSR_PMPADDR12, {"pmpaddr12", MISCREG_PMPADDR12}},
513    {CSR_PMPADDR13, {"pmpaddr13", MISCREG_PMPADDR13}},
514    {CSR_PMPADDR14, {"pmpaddr14", MISCREG_PMPADDR14}},
515    {CSR_PMPADDR15, {"pmpaddr15", MISCREG_PMPADDR15}},
516    {CSR_MCYCLE, {"mcycle", MISCREG_CYCLE}},
517    {CSR_MINSTRET, {"minstret", MISCREG_INSTRET}},
518    {CSR_MHPMCOUNTER03, {"mhpmcounter03", MISCREG_HPMCOUNTER03}},
519    {CSR_MHPMCOUNTER04, {"mhpmcounter04", MISCREG_HPMCOUNTER04}},
520    {CSR_MHPMCOUNTER05, {"mhpmcounter05", MISCREG_HPMCOUNTER05}},
521    {CSR_MHPMCOUNTER06, {"mhpmcounter06", MISCREG_HPMCOUNTER06}},
522    {CSR_MHPMCOUNTER07, {"mhpmcounter07", MISCREG_HPMCOUNTER07}},
523    {CSR_MHPMCOUNTER08, {"mhpmcounter08", MISCREG_HPMCOUNTER08}},
524    {CSR_MHPMCOUNTER09, {"mhpmcounter09", MISCREG_HPMCOUNTER09}},
525    {CSR_MHPMCOUNTER10, {"mhpmcounter10", MISCREG_HPMCOUNTER10}},
526    {CSR_MHPMCOUNTER11, {"mhpmcounter11", MISCREG_HPMCOUNTER11}},
527    {CSR_MHPMCOUNTER12, {"mhpmcounter12", MISCREG_HPMCOUNTER12}},
528    {CSR_MHPMCOUNTER13, {"mhpmcounter13", MISCREG_HPMCOUNTER13}},
529    {CSR_MHPMCOUNTER14, {"mhpmcounter14", MISCREG_HPMCOUNTER14}},
530    {CSR_MHPMCOUNTER15, {"mhpmcounter15", MISCREG_HPMCOUNTER15}},
531    {CSR_MHPMCOUNTER16, {"mhpmcounter16", MISCREG_HPMCOUNTER16}},
532    {CSR_MHPMCOUNTER17, {"mhpmcounter17", MISCREG_HPMCOUNTER17}},
533    {CSR_MHPMCOUNTER18, {"mhpmcounter18", MISCREG_HPMCOUNTER18}},
534    {CSR_MHPMCOUNTER19, {"mhpmcounter19", MISCREG_HPMCOUNTER19}},
535    {CSR_MHPMCOUNTER20, {"mhpmcounter20", MISCREG_HPMCOUNTER20}},
536    {CSR_MHPMCOUNTER21, {"mhpmcounter21", MISCREG_HPMCOUNTER21}},
537    {CSR_MHPMCOUNTER22, {"mhpmcounter22", MISCREG_HPMCOUNTER22}},
538    {CSR_MHPMCOUNTER23, {"mhpmcounter23", MISCREG_HPMCOUNTER23}},
539    {CSR_MHPMCOUNTER24, {"mhpmcounter24", MISCREG_HPMCOUNTER24}},
540    {CSR_MHPMCOUNTER25, {"mhpmcounter25", MISCREG_HPMCOUNTER25}},
541    {CSR_MHPMCOUNTER26, {"mhpmcounter26", MISCREG_HPMCOUNTER26}},
542    {CSR_MHPMCOUNTER27, {"mhpmcounter27", MISCREG_HPMCOUNTER27}},
543    {CSR_MHPMCOUNTER28, {"mhpmcounter28", MISCREG_HPMCOUNTER28}},
544    {CSR_MHPMCOUNTER29, {"mhpmcounter29", MISCREG_HPMCOUNTER29}},
545    {CSR_MHPMCOUNTER30, {"mhpmcounter30", MISCREG_HPMCOUNTER30}},
546    {CSR_MHPMCOUNTER31, {"mhpmcounter31", MISCREG_HPMCOUNTER31}},
547    {CSR_MHPMEVENT03, {"mhpmevent03", MISCREG_HPMEVENT03}},
548    {CSR_MHPMEVENT04, {"mhpmevent04", MISCREG_HPMEVENT04}},
549    {CSR_MHPMEVENT05, {"mhpmevent05", MISCREG_HPMEVENT05}},
550    {CSR_MHPMEVENT06, {"mhpmevent06", MISCREG_HPMEVENT06}},
551    {CSR_MHPMEVENT07, {"mhpmevent07", MISCREG_HPMEVENT07}},
552    {CSR_MHPMEVENT08, {"mhpmevent08", MISCREG_HPMEVENT08}},
553    {CSR_MHPMEVENT09, {"mhpmevent09", MISCREG_HPMEVENT09}},
554    {CSR_MHPMEVENT10, {"mhpmevent10", MISCREG_HPMEVENT10}},
555    {CSR_MHPMEVENT11, {"mhpmevent11", MISCREG_HPMEVENT11}},
556    {CSR_MHPMEVENT12, {"mhpmevent12", MISCREG_HPMEVENT12}},
557    {CSR_MHPMEVENT13, {"mhpmevent13", MISCREG_HPMEVENT13}},
558    {CSR_MHPMEVENT14, {"mhpmevent14", MISCREG_HPMEVENT14}},
559    {CSR_MHPMEVENT15, {"mhpmevent15", MISCREG_HPMEVENT15}},
560    {CSR_MHPMEVENT16, {"mhpmevent16", MISCREG_HPMEVENT16}},
561    {CSR_MHPMEVENT17, {"mhpmevent17", MISCREG_HPMEVENT17}},
562    {CSR_MHPMEVENT18, {"mhpmevent18", MISCREG_HPMEVENT18}},
563    {CSR_MHPMEVENT19, {"mhpmevent19", MISCREG_HPMEVENT19}},
564    {CSR_MHPMEVENT20, {"mhpmevent20", MISCREG_HPMEVENT20}},
565    {CSR_MHPMEVENT21, {"mhpmevent21", MISCREG_HPMEVENT21}},
566    {CSR_MHPMEVENT22, {"mhpmevent22", MISCREG_HPMEVENT22}},
567    {CSR_MHPMEVENT23, {"mhpmevent23", MISCREG_HPMEVENT23}},
568    {CSR_MHPMEVENT24, {"mhpmevent24", MISCREG_HPMEVENT24}},
569    {CSR_MHPMEVENT25, {"mhpmevent25", MISCREG_HPMEVENT25}},
570    {CSR_MHPMEVENT26, {"mhpmevent26", MISCREG_HPMEVENT26}},
571    {CSR_MHPMEVENT27, {"mhpmevent27", MISCREG_HPMEVENT27}},
572    {CSR_MHPMEVENT28, {"mhpmevent28", MISCREG_HPMEVENT28}},
573    {CSR_MHPMEVENT29, {"mhpmevent29", MISCREG_HPMEVENT29}},
574    {CSR_MHPMEVENT30, {"mhpmevent30", MISCREG_HPMEVENT30}},
575    {CSR_MHPMEVENT31, {"mhpmevent31", MISCREG_HPMEVENT31}},
576
577    {CSR_TSELECT, {"tselect", MISCREG_TSELECT}},
578    {CSR_TDATA1, {"tdata1", MISCREG_TDATA1}},
579    {CSR_TDATA2, {"tdata2", MISCREG_TDATA2}},
580    {CSR_TDATA3, {"tdata3", MISCREG_TDATA3}},
581    {CSR_DCSR, {"dcsr", MISCREG_DCSR}},
582    {CSR_DPC, {"dpc", MISCREG_DPC}},
583    {CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
584};
585
586/**
587 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
588 * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that
589 * uses these fields is the MSTATUS register, which is shadowed by two others
590 * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see
591 * the fields for higher privileges.
592 */
593BitUnion64(STATUS)
594    Bitfield<63> sd;
595    Bitfield<35, 34> sxl;
596    Bitfield<33, 32> uxl;
597    Bitfield<22> tsr;
598    Bitfield<21> tw;
599    Bitfield<20> tvm;
600    Bitfield<19> mxr;
601    Bitfield<18> sum;
602    Bitfield<17> mprv;
603    Bitfield<16, 15> xs;
604    Bitfield<14, 13> fs;
605    Bitfield<12, 11> mpp;
606    Bitfield<8> spp;
607    Bitfield<7> mpie;
608    Bitfield<5> spie;
609    Bitfield<4> upie;
610    Bitfield<3> mie;
611    Bitfield<1> sie;
612    Bitfield<0> uie;
613EndBitUnion(STATUS)
614
615/**
616 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
617 * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP
618 * and MIE registers have the same fields, so accesses to either should use
619 * this bit union.
620 */
621BitUnion64(INTERRUPT)
622    Bitfield<11> mei;
623    Bitfield<9> sei;
624    Bitfield<8> uei;
625    Bitfield<7> mti;
626    Bitfield<5> sti;
627    Bitfield<4> uti;
628    Bitfield<3> msi;
629    Bitfield<1> ssi;
630    Bitfield<0> usi;
631EndBitUnion(INTERRUPT)
632
633const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
634const off_t SXL_OFFSET = 34;
635const off_t UXL_OFFSET = 32;
636const off_t FS_OFFSET = 13;
637const off_t FRM_OFFSET = 5;
638
639const MiscReg ISA_MXL_MASK = 3ULL << MXL_OFFSET;
640const MiscReg ISA_EXT_MASK = mask(26);
641const MiscReg MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
642
643const MiscReg STATUS_SD_MASK = 1ULL << ((sizeof(MiscReg) * 8) - 1);
644const MiscReg STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
645const MiscReg STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
646const MiscReg STATUS_TSR_MASK = 1ULL << 22;
647const MiscReg STATUS_TW_MASK = 1ULL << 21;
648const MiscReg STATUS_TVM_MASK = 1ULL << 20;
649const MiscReg STATUS_MXR_MASK = 1ULL << 19;
650const MiscReg STATUS_SUM_MASK = 1ULL << 18;
651const MiscReg STATUS_MPRV_MASK = 1ULL << 17;
652const MiscReg STATUS_XS_MASK = 3ULL << 15;
653const MiscReg STATUS_FS_MASK = 3ULL << FS_OFFSET;
654const MiscReg STATUS_MPP_MASK = 3ULL << 11;
655const MiscReg STATUS_SPP_MASK = 1ULL << 8;
656const MiscReg STATUS_MPIE_MASK = 1ULL << 7;
657const MiscReg STATUS_SPIE_MASK = 1ULL << 5;
658const MiscReg STATUS_UPIE_MASK = 1ULL << 4;
659const MiscReg STATUS_MIE_MASK = 1ULL << 3;
660const MiscReg STATUS_SIE_MASK = 1ULL << 1;
661const MiscReg STATUS_UIE_MASK = 1ULL << 0;
662const MiscReg MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
663                             STATUS_UXL_MASK | STATUS_TSR_MASK |
664                             STATUS_TW_MASK | STATUS_TVM_MASK |
665                             STATUS_MXR_MASK | STATUS_SUM_MASK |
666                             STATUS_MPRV_MASK | STATUS_XS_MASK |
667                             STATUS_FS_MASK | STATUS_MPP_MASK |
668                             STATUS_SPP_MASK | STATUS_MPIE_MASK |
669                             STATUS_SPIE_MASK | STATUS_UPIE_MASK |
670                             STATUS_MIE_MASK | STATUS_SIE_MASK |
671                             STATUS_UIE_MASK;
672const MiscReg SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
673                             STATUS_MXR_MASK | STATUS_SUM_MASK |
674                             STATUS_XS_MASK | STATUS_FS_MASK |
675                             STATUS_SPP_MASK | STATUS_SPIE_MASK |
676                             STATUS_UPIE_MASK | STATUS_SIE_MASK |
677                             STATUS_UIE_MASK;
678const MiscReg USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
679                             STATUS_SUM_MASK | STATUS_XS_MASK |
680                             STATUS_FS_MASK | STATUS_UPIE_MASK |
681                             STATUS_UIE_MASK;
682
683const MiscReg MEI_MASK = 1ULL << 11;
684const MiscReg SEI_MASK = 1ULL << 9;
685const MiscReg UEI_MASK = 1ULL << 8;
686const MiscReg MTI_MASK = 1ULL << 7;
687const MiscReg STI_MASK = 1ULL << 5;
688const MiscReg UTI_MASK = 1ULL << 4;
689const MiscReg MSI_MASK = 1ULL << 3;
690const MiscReg SSI_MASK = 1ULL << 1;
691const MiscReg USI_MASK = 1ULL << 0;
692const MiscReg MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
693                        MTI_MASK | STI_MASK | UTI_MASK |
694                        MSI_MASK | SSI_MASK | USI_MASK;
695const MiscReg SI_MASK = SEI_MASK | UEI_MASK |
696                        STI_MASK | UTI_MASK |
697                        SSI_MASK | USI_MASK;
698const MiscReg UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
699const MiscReg FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
700const MiscReg FRM_MASK = 0x7;
701
702const std::map<int, MiscReg> CSRMasks = {
703    {CSR_USTATUS, USTATUS_MASK},
704    {CSR_UIE, UI_MASK},
705    {CSR_UIP, UI_MASK},
706    {CSR_FFLAGS, FFLAGS_MASK},
707    {CSR_FRM, FRM_MASK},
708    {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
709    {CSR_SSTATUS, SSTATUS_MASK},
710    {CSR_SIE, SI_MASK},
711    {CSR_SIP, SI_MASK},
712    {CSR_MSTATUS, MSTATUS_MASK},
713    {CSR_MISA, MISA_MASK},
714    {CSR_MIE, MI_MASK},
715    {CSR_MIP, MI_MASK}
716};
717
718}
719
720#endif // __ARCH_RISCV_REGISTERS_HH__
721