registers.hh revision 12413
1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2016 RISC-V Foundation 16 * Copyright (c) 2016 The University of Virginia 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Andreas Hansson 43 * Sven Karlsson 44 * Alec Roelke 45 */ 46 47#ifndef __ARCH_RISCV_REGISTERS_HH__ 48#define __ARCH_RISCV_REGISTERS_HH__ 49 50#include <map> 51#include <string> 52#include <vector> 53 54#include "arch/generic/types.hh" 55#include "arch/generic/vec_reg.hh" 56#include "arch/isa_traits.hh" 57#include "arch/riscv/generated/max_inst_regs.hh" 58#include "base/types.hh" 59 60namespace RiscvISA { 61 62using RiscvISAInst::MaxInstSrcRegs; 63using RiscvISAInst::MaxInstDestRegs; 64const int MaxMiscDestRegs = 1; 65 66typedef uint64_t IntReg; 67typedef uint64_t FloatRegBits; 68typedef double FloatReg; 69typedef uint8_t CCReg; // Not applicable to Riscv 70typedef uint64_t MiscReg; 71 72// dummy typedefs since we don't have vector regs 73const unsigned NumVecElemPerVecReg = 2; 74using VecElem = uint32_t; 75using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 76using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 77using VecRegContainer = VecReg::Container; 78 79const int NumIntArchRegs = 32; 80const int NumMicroIntRegs = 1; 81const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs; 82const int NumFloatRegs = 32; 83// This has to be one to prevent warnings that are treated as errors 84const unsigned NumVecRegs = 1; 85const int NumCCRegs = 0; 86const int NumMiscRegs = 4096; 87 88// Semantically meaningful register indices 89const int ZeroReg = 0; 90const int ReturnAddrReg = 1; 91const int StackPointerReg = 2; 92const int GlobalPointerReg = 3; 93const int ThreadPointerReg = 4; 94const int FramePointerReg = 8; 95const int ReturnValueReg = 10; 96const std::vector<int> ReturnValueRegs = {10, 11}; 97const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}; 98const int AMOTempReg = 32; 99 100const int SyscallPseudoReturnReg = 10; 101const std::vector<int> SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16}; 102const int SyscallNumReg = 17; 103 104const std::vector<std::string> IntRegNames = { 105 "zero", "ra", "sp", "gp", 106 "tp", "t0", "t1", "t2", 107 "s0", "s1", "a0", "a1", 108 "a2", "a3", "a4", "a5", 109 "a6", "a7", "s2", "s3", 110 "s4", "s5", "s6", "s7", 111 "s8", "s9", "s10", "s11", 112 "t3", "t4", "t5", "t6" 113}; 114const std::vector<std::string> FloatRegNames = { 115 "ft0", "ft1", "ft2", "ft3", 116 "ft4", "ft5", "ft6", "ft7", 117 "fs0", "fs1", "fa0", "fa1", 118 "fa2", "fa3", "fa4", "fa5", 119 "fa6", "fa7", "fs2", "fs3", 120 "fs4", "fs5", "fs6", "fs7", 121 "fs8", "fs9", "fs10", "fs11", 122 "ft8", "ft9", "ft10", "ft11" 123}; 124 125enum MiscRegIndex { 126 MISCREG_USTATUS = 0x000, 127 MISCREG_UIE = 0x004, 128 MISCREG_UTVEC = 0x005, 129 MISCREG_USCRATCH = 0x040, 130 MISCREG_UEPC = 0x041, 131 MISCREG_UCAUSE = 0x042, 132 MISCREG_UBADADDR = 0x043, 133 MISCREG_UIP = 0x044, 134 MISCREG_FFLAGS = 0x001, 135 MISCREG_FRM = 0x002, 136 MISCREG_FCSR = 0x003, 137 MISCREG_CYCLE = 0xC00, 138 MISCREG_TIME = 0xC01, 139 MISCREG_INSTRET = 0xC02, 140 MISCREG_HPMCOUNTER_BASE = 0xC03, 141 MISCREG_CYCLEH = 0xC80, 142 MISCREG_TIMEH = 0xC81, 143 MISCREG_INSTRETH = 0xC82, 144 MISCREG_HPMCOUNTERH_BASE = 0xC83, 145 146 MISCREG_SSTATUS = 0x100, 147 MISCREG_SEDELEG = 0x102, 148 MISCREG_SIDELEG = 0x103, 149 MISCREG_SIE = 0x104, 150 MISCREG_STVEC = 0x105, 151 MISCREG_SSCRATCH = 0x140, 152 MISCREG_SEPC = 0x141, 153 MISCREG_SCAUSE = 0x142, 154 MISCREG_SBADADDR = 0x143, 155 MISCREG_SIP = 0x144, 156 MISCREG_SPTBR = 0x180, 157 158 MISCREG_HSTATUS = 0x200, 159 MISCREG_HEDELEG = 0x202, 160 MISCREG_HIDELEG = 0x203, 161 MISCREG_HIE = 0x204, 162 MISCREG_HTVEC = 0x205, 163 MISCREG_HSCRATCH = 0x240, 164 MISCREG_HEPC = 0x241, 165 MISCREG_HCAUSE = 0x242, 166 MISCREG_HBADADDR = 0x243, 167 MISCREG_HIP = 0x244, 168 169 MISCREG_MVENDORID = 0xF11, 170 MISCREG_MARCHID = 0xF12, 171 MISCREG_MIMPID = 0xF13, 172 MISCREG_MHARTID = 0xF14, 173 MISCREG_MSTATUS = 0x300, 174 MISCREG_MISA = 0x301, 175 MISCREG_MEDELEG = 0x302, 176 MISCREG_MIDELEG = 0x303, 177 MISCREG_MIE = 0x304, 178 MISCREG_MTVEC = 0x305, 179 MISCREG_MSCRATCH = 0x340, 180 MISCREG_MEPC = 0x341, 181 MISCREG_MCAUSE = 0x342, 182 MISCREG_MBADADDR = 0x343, 183 MISCREG_MIP = 0x344, 184 MISCREG_MBASE = 0x380, 185 MISCREG_MBOUND = 0x381, 186 MISCREG_MIBASE = 0x382, 187 MISCREG_MIBOUND = 0x383, 188 MISCREG_MDBASE = 0x384, 189 MISCREG_MDBOUND = 0x385, 190 MISCREG_MCYCLE = 0xB00, 191 MISCREG_MINSTRET = 0xB02, 192 MISCREG_MHPMCOUNTER_BASE = 0xB03, 193 MISCREG_MUCOUNTEREN = 0x320, 194 MISCREG_MSCOUNTEREN = 0x321, 195 MISCREG_MHCOUNTEREN = 0x322, 196 MISCREG_MHPMEVENT_BASE = 0x323, 197 198 MISCREG_TSELECT = 0x7A0, 199 MISCREG_TDATA1 = 0x7A1, 200 MISCREG_TDATA2 = 0x7A2, 201 MISCREG_TDATA3 = 0x7A3, 202 MISCREG_DCSR = 0x7B0, 203 MISCREG_DPC = 0x7B1, 204 MISCREG_DSCRATCH = 0x7B2 205}; 206 207const std::map<int, std::string> MiscRegNames = { 208 {MISCREG_USTATUS, "ustatus"}, 209 {MISCREG_UIE, "uie"}, 210 {MISCREG_UTVEC, "utvec"}, 211 {MISCREG_USCRATCH, "uscratch"}, 212 {MISCREG_UEPC, "uepc"}, 213 {MISCREG_UCAUSE, "ucause"}, 214 {MISCREG_UBADADDR, "ubadaddr"}, 215 {MISCREG_UIP, "uip"}, 216 {MISCREG_FFLAGS, "fflags"}, 217 {MISCREG_FRM, "frm"}, 218 {MISCREG_FCSR, "fcsr"}, 219 {MISCREG_CYCLE, "cycle"}, 220 {MISCREG_TIME, "time"}, 221 {MISCREG_INSTRET, "instret"}, 222 {MISCREG_HPMCOUNTER_BASE + 0, "hpmcounter03"}, 223 {MISCREG_HPMCOUNTER_BASE + 1, "hpmcounter04"}, 224 {MISCREG_HPMCOUNTER_BASE + 2, "hpmcounter05"}, 225 {MISCREG_HPMCOUNTER_BASE + 3, "hpmcounter06"}, 226 {MISCREG_HPMCOUNTER_BASE + 4, "hpmcounter07"}, 227 {MISCREG_HPMCOUNTER_BASE + 5, "hpmcounter08"}, 228 {MISCREG_HPMCOUNTER_BASE + 6, "hpmcounter09"}, 229 {MISCREG_HPMCOUNTER_BASE + 7, "hpmcounter10"}, 230 {MISCREG_HPMCOUNTER_BASE + 8, "hpmcounter11"}, 231 {MISCREG_HPMCOUNTER_BASE + 9, "hpmcounter12"}, 232 {MISCREG_HPMCOUNTER_BASE + 10, "hpmcounter13"}, 233 {MISCREG_HPMCOUNTER_BASE + 11, "hpmcounter14"}, 234 {MISCREG_HPMCOUNTER_BASE + 12, "hpmcounter15"}, 235 {MISCREG_HPMCOUNTER_BASE + 13, "hpmcounter16"}, 236 {MISCREG_HPMCOUNTER_BASE + 14, "hpmcounter17"}, 237 {MISCREG_HPMCOUNTER_BASE + 15, "hpmcounter18"}, 238 {MISCREG_HPMCOUNTER_BASE + 16, "hpmcounter19"}, 239 {MISCREG_HPMCOUNTER_BASE + 17, "hpmcounter20"}, 240 {MISCREG_HPMCOUNTER_BASE + 18, "hpmcounter21"}, 241 {MISCREG_HPMCOUNTER_BASE + 19, "hpmcounter22"}, 242 {MISCREG_HPMCOUNTER_BASE + 20, "hpmcounter23"}, 243 {MISCREG_HPMCOUNTER_BASE + 21, "hpmcounter24"}, 244 {MISCREG_HPMCOUNTER_BASE + 22, "hpmcounter25"}, 245 {MISCREG_HPMCOUNTER_BASE + 23, "hpmcounter26"}, 246 {MISCREG_HPMCOUNTER_BASE + 24, "hpmcounter27"}, 247 {MISCREG_HPMCOUNTER_BASE + 25, "hpmcounter28"}, 248 {MISCREG_HPMCOUNTER_BASE + 26, "hpmcounter29"}, 249 {MISCREG_HPMCOUNTER_BASE + 27, "hpmcounter30"}, 250 {MISCREG_HPMCOUNTER_BASE + 28, "hpmcounter31"}, 251 {MISCREG_CYCLEH, "cycleh"}, 252 {MISCREG_TIMEH, "timeh"}, 253 {MISCREG_INSTRETH, "instreth"}, 254 {MISCREG_HPMCOUNTERH_BASE + 0, "hpmcounterh03"}, 255 {MISCREG_HPMCOUNTERH_BASE + 1, "hpmcounterh04"}, 256 {MISCREG_HPMCOUNTERH_BASE + 2, "hpmcounterh05"}, 257 {MISCREG_HPMCOUNTERH_BASE + 3, "hpmcounterh06"}, 258 {MISCREG_HPMCOUNTERH_BASE + 4, "hpmcounterh07"}, 259 {MISCREG_HPMCOUNTERH_BASE + 5, "hpmcounterh08"}, 260 {MISCREG_HPMCOUNTERH_BASE + 6, "hpmcounterh09"}, 261 {MISCREG_HPMCOUNTERH_BASE + 7, "hpmcounterh10"}, 262 {MISCREG_HPMCOUNTERH_BASE + 8, "hpmcounterh11"}, 263 {MISCREG_HPMCOUNTERH_BASE + 9, "hpmcounterh12"}, 264 {MISCREG_HPMCOUNTERH_BASE + 10, "hpmcounterh13"}, 265 {MISCREG_HPMCOUNTERH_BASE + 11, "hpmcounterh14"}, 266 {MISCREG_HPMCOUNTERH_BASE + 12, "hpmcounterh15"}, 267 {MISCREG_HPMCOUNTERH_BASE + 13, "hpmcounterh16"}, 268 {MISCREG_HPMCOUNTERH_BASE + 14, "hpmcounterh17"}, 269 {MISCREG_HPMCOUNTERH_BASE + 15, "hpmcounterh18"}, 270 {MISCREG_HPMCOUNTERH_BASE + 16, "hpmcounterh19"}, 271 {MISCREG_HPMCOUNTERH_BASE + 17, "hpmcounterh20"}, 272 {MISCREG_HPMCOUNTERH_BASE + 18, "hpmcounterh21"}, 273 {MISCREG_HPMCOUNTERH_BASE + 19, "hpmcounterh22"}, 274 {MISCREG_HPMCOUNTERH_BASE + 20, "hpmcounterh23"}, 275 {MISCREG_HPMCOUNTERH_BASE + 21, "hpmcounterh24"}, 276 {MISCREG_HPMCOUNTERH_BASE + 22, "hpmcounterh25"}, 277 {MISCREG_HPMCOUNTERH_BASE + 23, "hpmcounterh26"}, 278 {MISCREG_HPMCOUNTERH_BASE + 24, "hpmcounterh27"}, 279 {MISCREG_HPMCOUNTERH_BASE + 25, "hpmcounterh28"}, 280 {MISCREG_HPMCOUNTERH_BASE + 26, "hpmcounterh29"}, 281 {MISCREG_HPMCOUNTERH_BASE + 27, "hpmcounterh30"}, 282 {MISCREG_HPMCOUNTERH_BASE + 28, "hpmcounterh31"}, 283 284 {MISCREG_SSTATUS, "sstatus"}, 285 {MISCREG_SEDELEG, "sedeleg"}, 286 {MISCREG_SIDELEG, "sideleg"}, 287 {MISCREG_SIE, "sie"}, 288 {MISCREG_STVEC, "stvec"}, 289 {MISCREG_SSCRATCH, "sscratch"}, 290 {MISCREG_SEPC, "sepc"}, 291 {MISCREG_SCAUSE, "scause"}, 292 {MISCREG_SBADADDR, "sbadaddr"}, 293 {MISCREG_SIP, "sip"}, 294 {MISCREG_SPTBR, "sptbr"}, 295 296 {MISCREG_HSTATUS, "hstatus"}, 297 {MISCREG_HEDELEG, "hedeleg"}, 298 {MISCREG_HIDELEG, "hideleg"}, 299 {MISCREG_HIE, "hie"}, 300 {MISCREG_HTVEC, "htvec"}, 301 {MISCREG_HSCRATCH, "hscratch"}, 302 {MISCREG_HEPC, "hepc"}, 303 {MISCREG_HCAUSE, "hcause"}, 304 {MISCREG_HBADADDR, "hbadaddr"}, 305 {MISCREG_HIP, "hip"}, 306 307 {MISCREG_MVENDORID, "mvendorid"}, 308 {MISCREG_MARCHID, "marchid"}, 309 {MISCREG_MIMPID, "mimpid"}, 310 {MISCREG_MHARTID, "mhartid"}, 311 {MISCREG_MSTATUS, "mstatus"}, 312 {MISCREG_MISA, "misa"}, 313 {MISCREG_MEDELEG, "medeleg"}, 314 {MISCREG_MIDELEG, "mideleg"}, 315 {MISCREG_MIE, "mie"}, 316 {MISCREG_MTVEC, "mtvec"}, 317 {MISCREG_MSCRATCH, "mscratch"}, 318 {MISCREG_MEPC, "mepc"}, 319 {MISCREG_MCAUSE, "mcause"}, 320 {MISCREG_MBADADDR, "mbadaddr"}, 321 {MISCREG_MIP, "mip"}, 322 {MISCREG_MBASE, "mbase"}, 323 {MISCREG_MBOUND, "mbound"}, 324 {MISCREG_MIBASE, "mibase"}, 325 {MISCREG_MIBOUND, "mibound"}, 326 {MISCREG_MDBASE, "mdbase"}, 327 {MISCREG_MDBOUND, "mdbound"}, 328 {MISCREG_MCYCLE, "mcycle"}, 329 {MISCREG_MINSTRET, "minstret"}, 330 {MISCREG_MHPMCOUNTER_BASE + 0, "mhpmcounter03"}, 331 {MISCREG_MHPMCOUNTER_BASE + 1, "mhpmcounter04"}, 332 {MISCREG_MHPMCOUNTER_BASE + 2, "mhpmcounter05"}, 333 {MISCREG_MHPMCOUNTER_BASE + 3, "mhpmcounter06"}, 334 {MISCREG_MHPMCOUNTER_BASE + 4, "mhpmcounter07"}, 335 {MISCREG_MHPMCOUNTER_BASE + 5, "mhpmcounter08"}, 336 {MISCREG_MHPMCOUNTER_BASE + 6, "mhpmcounter09"}, 337 {MISCREG_MHPMCOUNTER_BASE + 7, "mhpmcounter10"}, 338 {MISCREG_MHPMCOUNTER_BASE + 8, "mhpmcounter11"}, 339 {MISCREG_MHPMCOUNTER_BASE + 9, "mhpmcounter12"}, 340 {MISCREG_MHPMCOUNTER_BASE + 10, "mhpmcounter13"}, 341 {MISCREG_MHPMCOUNTER_BASE + 11, "mhpmcounter14"}, 342 {MISCREG_MHPMCOUNTER_BASE + 12, "mhpmcounter15"}, 343 {MISCREG_MHPMCOUNTER_BASE + 13, "mhpmcounter16"}, 344 {MISCREG_MHPMCOUNTER_BASE + 14, "mhpmcounter17"}, 345 {MISCREG_MHPMCOUNTER_BASE + 15, "mhpmcounter18"}, 346 {MISCREG_MHPMCOUNTER_BASE + 16, "mhpmcounter19"}, 347 {MISCREG_MHPMCOUNTER_BASE + 17, "mhpmcounter20"}, 348 {MISCREG_MHPMCOUNTER_BASE + 18, "mhpmcounter21"}, 349 {MISCREG_MHPMCOUNTER_BASE + 19, "mhpmcounter22"}, 350 {MISCREG_MHPMCOUNTER_BASE + 20, "mhpmcounter23"}, 351 {MISCREG_MHPMCOUNTER_BASE + 21, "mhpmcounter24"}, 352 {MISCREG_MHPMCOUNTER_BASE + 22, "mhpmcounter25"}, 353 {MISCREG_MHPMCOUNTER_BASE + 23, "mhpmcounter26"}, 354 {MISCREG_MHPMCOUNTER_BASE + 24, "mhpmcounter27"}, 355 {MISCREG_MHPMCOUNTER_BASE + 25, "mhpmcounter28"}, 356 {MISCREG_MHPMCOUNTER_BASE + 26, "mhpmcounter29"}, 357 {MISCREG_MHPMCOUNTER_BASE + 27, "mhpmcounter30"}, 358 {MISCREG_MHPMCOUNTER_BASE + 28, "mhpmcounter31"}, 359 {MISCREG_MUCOUNTEREN, "mucounteren"}, 360 {MISCREG_MSCOUNTEREN, "mscounteren"}, 361 {MISCREG_MHCOUNTEREN, "mhcounteren"}, 362 {MISCREG_MHPMEVENT_BASE + 0, "mhpmevent03"}, 363 {MISCREG_MHPMEVENT_BASE + 1, "mhpmevent04"}, 364 {MISCREG_MHPMEVENT_BASE + 2, "mhpmevent05"}, 365 {MISCREG_MHPMEVENT_BASE + 3, "mhpmevent06"}, 366 {MISCREG_MHPMEVENT_BASE + 4, "mhpmevent07"}, 367 {MISCREG_MHPMEVENT_BASE + 5, "mhpmevent08"}, 368 {MISCREG_MHPMEVENT_BASE + 6, "mhpmevent09"}, 369 {MISCREG_MHPMEVENT_BASE + 7, "mhpmevent10"}, 370 {MISCREG_MHPMEVENT_BASE + 8, "mhpmevent11"}, 371 {MISCREG_MHPMEVENT_BASE + 9, "mhpmevent12"}, 372 {MISCREG_MHPMEVENT_BASE + 10, "mhpmevent13"}, 373 {MISCREG_MHPMEVENT_BASE + 11, "mhpmevent14"}, 374 {MISCREG_MHPMEVENT_BASE + 12, "mhpmevent15"}, 375 {MISCREG_MHPMEVENT_BASE + 13, "mhpmevent16"}, 376 {MISCREG_MHPMEVENT_BASE + 14, "mhpmevent17"}, 377 {MISCREG_MHPMEVENT_BASE + 15, "mhpmevent18"}, 378 {MISCREG_MHPMEVENT_BASE + 16, "mhpmevent19"}, 379 {MISCREG_MHPMEVENT_BASE + 17, "mhpmevent20"}, 380 {MISCREG_MHPMEVENT_BASE + 18, "mhpmevent21"}, 381 {MISCREG_MHPMEVENT_BASE + 19, "mhpmevent22"}, 382 {MISCREG_MHPMEVENT_BASE + 20, "mhpmevent23"}, 383 {MISCREG_MHPMEVENT_BASE + 21, "mhpmevent24"}, 384 {MISCREG_MHPMEVENT_BASE + 22, "mhpmevent25"}, 385 {MISCREG_MHPMEVENT_BASE + 23, "mhpmevent26"}, 386 {MISCREG_MHPMEVENT_BASE + 24, "mhpmevent27"}, 387 {MISCREG_MHPMEVENT_BASE + 25, "mhpmevent28"}, 388 {MISCREG_MHPMEVENT_BASE + 26, "mhpmevent29"}, 389 {MISCREG_MHPMEVENT_BASE + 27, "mhpmevent30"}, 390 {MISCREG_MHPMEVENT_BASE + 28, "mhpmevent31"}, 391 392 {MISCREG_TSELECT, "tselect"}, 393 {MISCREG_TDATA1, "tdata1"}, 394 {MISCREG_TDATA2, "tdata2"}, 395 {MISCREG_TDATA3, "tdata3"}, 396 {MISCREG_DCSR, "dcsr"}, 397 {MISCREG_DPC, "dpc"}, 398 {MISCREG_DSCRATCH, "dscratch"} 399}; 400 401} 402 403#endif // __ARCH_RISCV_REGISTERS_HH__ 404