registers.hh revision 12135:44bd81faf754
1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2016 RISC-V Foundation 16 * Copyright (c) 2016 The University of Virginia 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Andreas Hansson 43 * Sven Karlsson 44 * Alec Roelke 45 */ 46 47#ifndef __ARCH_RISCV_REGISTERS_HH__ 48#define __ARCH_RISCV_REGISTERS_HH__ 49 50#include <map> 51#include <string> 52#include <vector> 53 54#include "arch/generic/types.hh" 55#include "arch/generic/vec_reg.hh" 56#include "arch/isa_traits.hh" 57#include "arch/riscv/generated/max_inst_regs.hh" 58#include "base/types.hh" 59 60namespace RiscvISA { 61 62using RiscvISAInst::MaxInstSrcRegs; 63using RiscvISAInst::MaxInstDestRegs; 64const int MaxMiscDestRegs = 1; 65 66typedef uint64_t IntReg; 67typedef uint64_t FloatRegBits; 68typedef double FloatReg; 69typedef uint8_t CCReg; // Not applicable to Riscv 70typedef uint64_t MiscReg; 71 72// dummy typedefs since we don't have vector regs 73const unsigned NumVecElemPerVecReg = 2; 74using VecElem = uint32_t; 75using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 76using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 77using VecRegContainer = VecReg::Container; 78 79const int NumIntArchRegs = 32; 80const int NumMicroIntRegs = 1; 81const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs; 82const int NumFloatRegs = 32; 83// This has to be one to prevent warnings that are treated as errors 84const unsigned NumVecRegs = 1; 85const int NumCCRegs = 0; 86const int NumMiscRegs = 4096; 87 88// Semantically meaningful register indices 89const int ZeroReg = 0; 90const int ReturnAddrReg = 1; 91const int StackPointerReg = 2; 92const int GlobalPointerReg = 3; 93const int ThreadPointerReg = 4; 94const int FramePointerReg = 8; 95const std::vector<int> ReturnValueRegs = {10, 11}; 96const int ReturnValueReg M5_VAR_USED = ReturnValueRegs[0]; 97const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}; 98const int AMOTempReg = 32; 99 100const std::vector<std::string> IntRegNames = { 101 "zero", "ra", "sp", "gp", 102 "tp", "t0", "t1", "t2", 103 "s0", "s1", "a0", "a1", 104 "a2", "a3", "a4", "a5", 105 "a6", "a7", "s2", "s3", 106 "s4", "s5", "s6", "s7", 107 "s8", "s9", "s10", "s11", 108 "t3", "t4", "t5", "t6" 109}; 110const std::vector<std::string> FloatRegNames = { 111 "ft0", "ft1", "ft2", "ft3", 112 "ft4", "ft5", "ft6", "ft7", 113 "fs0", "fs1", "fa0", "fa1", 114 "fa2", "fa3", "fa4", "fa5", 115 "fa6", "fa7", "fs2", "fs3", 116 "fs4", "fs5", "fs6", "fs7", 117 "fs8", "fs9", "fs10", "fs11", 118 "ft8", "ft9", "ft10", "ft11" 119}; 120 121const int SyscallNumReg M5_VAR_USED = ArgumentRegs[7]; 122const std::vector<int> SyscallArgumentRegs = {ArgumentRegs[0], ArgumentRegs[1], 123 ArgumentRegs[2], ArgumentRegs[3]}; 124const int SyscallPseudoReturnReg M5_VAR_USED = ReturnValueRegs[0]; 125 126enum MiscRegIndex { 127 MISCREG_USTATUS = 0x000, 128 MISCREG_UIE = 0x004, 129 MISCREG_UTVEC = 0x005, 130 MISCREG_USCRATCH = 0x040, 131 MISCREG_UEPC = 0x041, 132 MISCREG_UCAUSE = 0x042, 133 MISCREG_UBADADDR = 0x043, 134 MISCREG_UIP = 0x044, 135 MISCREG_FFLAGS = 0x001, 136 MISCREG_FRM = 0x002, 137 MISCREG_FCSR = 0x003, 138 MISCREG_CYCLE = 0xC00, 139 MISCREG_TIME = 0xC01, 140 MISCREG_INSTRET = 0xC02, 141 MISCREG_HPMCOUNTER_BASE = 0xC03, 142 MISCREG_CYCLEH = 0xC80, 143 MISCREG_TIMEH = 0xC81, 144 MISCREG_INSTRETH = 0xC82, 145 MISCREG_HPMCOUNTERH_BASE = 0xC83, 146 147 MISCREG_SSTATUS = 0x100, 148 MISCREG_SEDELEG = 0x102, 149 MISCREG_SIDELEG = 0x103, 150 MISCREG_SIE = 0x104, 151 MISCREG_STVEC = 0x105, 152 MISCREG_SSCRATCH = 0x140, 153 MISCREG_SEPC = 0x141, 154 MISCREG_SCAUSE = 0x142, 155 MISCREG_SBADADDR = 0x143, 156 MISCREG_SIP = 0x144, 157 MISCREG_SPTBR = 0x180, 158 159 MISCREG_HSTATUS = 0x200, 160 MISCREG_HEDELEG = 0x202, 161 MISCREG_HIDELEG = 0x203, 162 MISCREG_HIE = 0x204, 163 MISCREG_HTVEC = 0x205, 164 MISCREG_HSCRATCH = 0x240, 165 MISCREG_HEPC = 0x241, 166 MISCREG_HCAUSE = 0x242, 167 MISCREG_HBADADDR = 0x243, 168 MISCREG_HIP = 0x244, 169 170 MISCREG_MVENDORID = 0xF11, 171 MISCREG_MARCHID = 0xF12, 172 MISCREG_MIMPID = 0xF13, 173 MISCREG_MHARTID = 0xF14, 174 MISCREG_MSTATUS = 0x300, 175 MISCREG_MISA = 0x301, 176 MISCREG_MEDELEG = 0x302, 177 MISCREG_MIDELEG = 0x303, 178 MISCREG_MIE = 0x304, 179 MISCREG_MTVEC = 0x305, 180 MISCREG_MSCRATCH = 0x340, 181 MISCREG_MEPC = 0x341, 182 MISCREG_MCAUSE = 0x342, 183 MISCREG_MBADADDR = 0x343, 184 MISCREG_MIP = 0x344, 185 MISCREG_MBASE = 0x380, 186 MISCREG_MBOUND = 0x381, 187 MISCREG_MIBASE = 0x382, 188 MISCREG_MIBOUND = 0x383, 189 MISCREG_MDBASE = 0x384, 190 MISCREG_MDBOUND = 0x385, 191 MISCREG_MCYCLE = 0xB00, 192 MISCREG_MINSTRET = 0xB02, 193 MISCREG_MHPMCOUNTER_BASE = 0xB03, 194 MISCREG_MUCOUNTEREN = 0x320, 195 MISCREG_MSCOUNTEREN = 0x321, 196 MISCREG_MHCOUNTEREN = 0x322, 197 MISCREG_MHPMEVENT_BASE = 0x323, 198 199 MISCREG_TSELECT = 0x7A0, 200 MISCREG_TDATA1 = 0x7A1, 201 MISCREG_TDATA2 = 0x7A2, 202 MISCREG_TDATA3 = 0x7A3, 203 MISCREG_DCSR = 0x7B0, 204 MISCREG_DPC = 0x7B1, 205 MISCREG_DSCRATCH = 0x7B2 206}; 207 208const std::map<int, std::string> MiscRegNames = { 209 {MISCREG_USTATUS, "ustatus"}, 210 {MISCREG_UIE, "uie"}, 211 {MISCREG_UTVEC, "utvec"}, 212 {MISCREG_USCRATCH, "uscratch"}, 213 {MISCREG_UEPC, "uepc"}, 214 {MISCREG_UCAUSE, "ucause"}, 215 {MISCREG_UBADADDR, "ubadaddr"}, 216 {MISCREG_UIP, "uip"}, 217 {MISCREG_FFLAGS, "fflags"}, 218 {MISCREG_FRM, "frm"}, 219 {MISCREG_FCSR, "fcsr"}, 220 {MISCREG_CYCLE, "cycle"}, 221 {MISCREG_TIME, "time"}, 222 {MISCREG_INSTRET, "instret"}, 223 {MISCREG_HPMCOUNTER_BASE + 0, "hpmcounter03"}, 224 {MISCREG_HPMCOUNTER_BASE + 1, "hpmcounter04"}, 225 {MISCREG_HPMCOUNTER_BASE + 2, "hpmcounter05"}, 226 {MISCREG_HPMCOUNTER_BASE + 3, "hpmcounter06"}, 227 {MISCREG_HPMCOUNTER_BASE + 4, "hpmcounter07"}, 228 {MISCREG_HPMCOUNTER_BASE + 5, "hpmcounter08"}, 229 {MISCREG_HPMCOUNTER_BASE + 6, "hpmcounter09"}, 230 {MISCREG_HPMCOUNTER_BASE + 7, "hpmcounter10"}, 231 {MISCREG_HPMCOUNTER_BASE + 8, "hpmcounter11"}, 232 {MISCREG_HPMCOUNTER_BASE + 9, "hpmcounter12"}, 233 {MISCREG_HPMCOUNTER_BASE + 10, "hpmcounter13"}, 234 {MISCREG_HPMCOUNTER_BASE + 11, "hpmcounter14"}, 235 {MISCREG_HPMCOUNTER_BASE + 12, "hpmcounter15"}, 236 {MISCREG_HPMCOUNTER_BASE + 13, "hpmcounter16"}, 237 {MISCREG_HPMCOUNTER_BASE + 14, "hpmcounter17"}, 238 {MISCREG_HPMCOUNTER_BASE + 15, "hpmcounter18"}, 239 {MISCREG_HPMCOUNTER_BASE + 16, "hpmcounter19"}, 240 {MISCREG_HPMCOUNTER_BASE + 17, "hpmcounter20"}, 241 {MISCREG_HPMCOUNTER_BASE + 18, "hpmcounter21"}, 242 {MISCREG_HPMCOUNTER_BASE + 19, "hpmcounter22"}, 243 {MISCREG_HPMCOUNTER_BASE + 20, "hpmcounter23"}, 244 {MISCREG_HPMCOUNTER_BASE + 21, "hpmcounter24"}, 245 {MISCREG_HPMCOUNTER_BASE + 22, "hpmcounter25"}, 246 {MISCREG_HPMCOUNTER_BASE + 23, "hpmcounter26"}, 247 {MISCREG_HPMCOUNTER_BASE + 24, "hpmcounter27"}, 248 {MISCREG_HPMCOUNTER_BASE + 25, "hpmcounter28"}, 249 {MISCREG_HPMCOUNTER_BASE + 26, "hpmcounter29"}, 250 {MISCREG_HPMCOUNTER_BASE + 27, "hpmcounter30"}, 251 {MISCREG_HPMCOUNTER_BASE + 28, "hpmcounter31"}, 252 {MISCREG_CYCLEH, "cycleh"}, 253 {MISCREG_TIMEH, "timeh"}, 254 {MISCREG_INSTRETH, "instreth"}, 255 {MISCREG_HPMCOUNTERH_BASE + 0, "hpmcounterh03"}, 256 {MISCREG_HPMCOUNTERH_BASE + 1, "hpmcounterh04"}, 257 {MISCREG_HPMCOUNTERH_BASE + 2, "hpmcounterh05"}, 258 {MISCREG_HPMCOUNTERH_BASE + 3, "hpmcounterh06"}, 259 {MISCREG_HPMCOUNTERH_BASE + 4, "hpmcounterh07"}, 260 {MISCREG_HPMCOUNTERH_BASE + 5, "hpmcounterh08"}, 261 {MISCREG_HPMCOUNTERH_BASE + 6, "hpmcounterh09"}, 262 {MISCREG_HPMCOUNTERH_BASE + 7, "hpmcounterh10"}, 263 {MISCREG_HPMCOUNTERH_BASE + 8, "hpmcounterh11"}, 264 {MISCREG_HPMCOUNTERH_BASE + 9, "hpmcounterh12"}, 265 {MISCREG_HPMCOUNTERH_BASE + 10, "hpmcounterh13"}, 266 {MISCREG_HPMCOUNTERH_BASE + 11, "hpmcounterh14"}, 267 {MISCREG_HPMCOUNTERH_BASE + 12, "hpmcounterh15"}, 268 {MISCREG_HPMCOUNTERH_BASE + 13, "hpmcounterh16"}, 269 {MISCREG_HPMCOUNTERH_BASE + 14, "hpmcounterh17"}, 270 {MISCREG_HPMCOUNTERH_BASE + 15, "hpmcounterh18"}, 271 {MISCREG_HPMCOUNTERH_BASE + 16, "hpmcounterh19"}, 272 {MISCREG_HPMCOUNTERH_BASE + 17, "hpmcounterh20"}, 273 {MISCREG_HPMCOUNTERH_BASE + 18, "hpmcounterh21"}, 274 {MISCREG_HPMCOUNTERH_BASE + 19, "hpmcounterh22"}, 275 {MISCREG_HPMCOUNTERH_BASE + 20, "hpmcounterh23"}, 276 {MISCREG_HPMCOUNTERH_BASE + 21, "hpmcounterh24"}, 277 {MISCREG_HPMCOUNTERH_BASE + 22, "hpmcounterh25"}, 278 {MISCREG_HPMCOUNTERH_BASE + 23, "hpmcounterh26"}, 279 {MISCREG_HPMCOUNTERH_BASE + 24, "hpmcounterh27"}, 280 {MISCREG_HPMCOUNTERH_BASE + 25, "hpmcounterh28"}, 281 {MISCREG_HPMCOUNTERH_BASE + 26, "hpmcounterh29"}, 282 {MISCREG_HPMCOUNTERH_BASE + 27, "hpmcounterh30"}, 283 {MISCREG_HPMCOUNTERH_BASE + 28, "hpmcounterh31"}, 284 285 {MISCREG_SSTATUS, "sstatus"}, 286 {MISCREG_SEDELEG, "sedeleg"}, 287 {MISCREG_SIDELEG, "sideleg"}, 288 {MISCREG_SIE, "sie"}, 289 {MISCREG_STVEC, "stvec"}, 290 {MISCREG_SSCRATCH, "sscratch"}, 291 {MISCREG_SEPC, "sepc"}, 292 {MISCREG_SCAUSE, "scause"}, 293 {MISCREG_SBADADDR, "sbadaddr"}, 294 {MISCREG_SIP, "sip"}, 295 {MISCREG_SPTBR, "sptbr"}, 296 297 {MISCREG_HSTATUS, "hstatus"}, 298 {MISCREG_HEDELEG, "hedeleg"}, 299 {MISCREG_HIDELEG, "hideleg"}, 300 {MISCREG_HIE, "hie"}, 301 {MISCREG_HTVEC, "htvec"}, 302 {MISCREG_HSCRATCH, "hscratch"}, 303 {MISCREG_HEPC, "hepc"}, 304 {MISCREG_HCAUSE, "hcause"}, 305 {MISCREG_HBADADDR, "hbadaddr"}, 306 {MISCREG_HIP, "hip"}, 307 308 {MISCREG_MVENDORID, "mvendorid"}, 309 {MISCREG_MARCHID, "marchid"}, 310 {MISCREG_MIMPID, "mimpid"}, 311 {MISCREG_MHARTID, "mhartid"}, 312 {MISCREG_MSTATUS, "mstatus"}, 313 {MISCREG_MISA, "misa"}, 314 {MISCREG_MEDELEG, "medeleg"}, 315 {MISCREG_MIDELEG, "mideleg"}, 316 {MISCREG_MIE, "mie"}, 317 {MISCREG_MTVEC, "mtvec"}, 318 {MISCREG_MSCRATCH, "mscratch"}, 319 {MISCREG_MEPC, "mepc"}, 320 {MISCREG_MCAUSE, "mcause"}, 321 {MISCREG_MBADADDR, "mbadaddr"}, 322 {MISCREG_MIP, "mip"}, 323 {MISCREG_MBASE, "mbase"}, 324 {MISCREG_MBOUND, "mbound"}, 325 {MISCREG_MIBASE, "mibase"}, 326 {MISCREG_MIBOUND, "mibound"}, 327 {MISCREG_MDBASE, "mdbase"}, 328 {MISCREG_MDBOUND, "mdbound"}, 329 {MISCREG_MCYCLE, "mcycle"}, 330 {MISCREG_MINSTRET, "minstret"}, 331 {MISCREG_MHPMCOUNTER_BASE + 0, "mhpmcounter03"}, 332 {MISCREG_MHPMCOUNTER_BASE + 1, "mhpmcounter04"}, 333 {MISCREG_MHPMCOUNTER_BASE + 2, "mhpmcounter05"}, 334 {MISCREG_MHPMCOUNTER_BASE + 3, "mhpmcounter06"}, 335 {MISCREG_MHPMCOUNTER_BASE + 4, "mhpmcounter07"}, 336 {MISCREG_MHPMCOUNTER_BASE + 5, "mhpmcounter08"}, 337 {MISCREG_MHPMCOUNTER_BASE + 6, "mhpmcounter09"}, 338 {MISCREG_MHPMCOUNTER_BASE + 7, "mhpmcounter10"}, 339 {MISCREG_MHPMCOUNTER_BASE + 8, "mhpmcounter11"}, 340 {MISCREG_MHPMCOUNTER_BASE + 9, "mhpmcounter12"}, 341 {MISCREG_MHPMCOUNTER_BASE + 10, "mhpmcounter13"}, 342 {MISCREG_MHPMCOUNTER_BASE + 11, "mhpmcounter14"}, 343 {MISCREG_MHPMCOUNTER_BASE + 12, "mhpmcounter15"}, 344 {MISCREG_MHPMCOUNTER_BASE + 13, "mhpmcounter16"}, 345 {MISCREG_MHPMCOUNTER_BASE + 14, "mhpmcounter17"}, 346 {MISCREG_MHPMCOUNTER_BASE + 15, "mhpmcounter18"}, 347 {MISCREG_MHPMCOUNTER_BASE + 16, "mhpmcounter19"}, 348 {MISCREG_MHPMCOUNTER_BASE + 17, "mhpmcounter20"}, 349 {MISCREG_MHPMCOUNTER_BASE + 18, "mhpmcounter21"}, 350 {MISCREG_MHPMCOUNTER_BASE + 19, "mhpmcounter22"}, 351 {MISCREG_MHPMCOUNTER_BASE + 20, "mhpmcounter23"}, 352 {MISCREG_MHPMCOUNTER_BASE + 21, "mhpmcounter24"}, 353 {MISCREG_MHPMCOUNTER_BASE + 22, "mhpmcounter25"}, 354 {MISCREG_MHPMCOUNTER_BASE + 23, "mhpmcounter26"}, 355 {MISCREG_MHPMCOUNTER_BASE + 24, "mhpmcounter27"}, 356 {MISCREG_MHPMCOUNTER_BASE + 25, "mhpmcounter28"}, 357 {MISCREG_MHPMCOUNTER_BASE + 26, "mhpmcounter29"}, 358 {MISCREG_MHPMCOUNTER_BASE + 27, "mhpmcounter30"}, 359 {MISCREG_MHPMCOUNTER_BASE + 28, "mhpmcounter31"}, 360 {MISCREG_MUCOUNTEREN, "mucounteren"}, 361 {MISCREG_MSCOUNTEREN, "mscounteren"}, 362 {MISCREG_MHCOUNTEREN, "mhcounteren"}, 363 {MISCREG_MHPMEVENT_BASE + 0, "mhpmevent03"}, 364 {MISCREG_MHPMEVENT_BASE + 1, "mhpmevent04"}, 365 {MISCREG_MHPMEVENT_BASE + 2, "mhpmevent05"}, 366 {MISCREG_MHPMEVENT_BASE + 3, "mhpmevent06"}, 367 {MISCREG_MHPMEVENT_BASE + 4, "mhpmevent07"}, 368 {MISCREG_MHPMEVENT_BASE + 5, "mhpmevent08"}, 369 {MISCREG_MHPMEVENT_BASE + 6, "mhpmevent09"}, 370 {MISCREG_MHPMEVENT_BASE + 7, "mhpmevent10"}, 371 {MISCREG_MHPMEVENT_BASE + 8, "mhpmevent11"}, 372 {MISCREG_MHPMEVENT_BASE + 9, "mhpmevent12"}, 373 {MISCREG_MHPMEVENT_BASE + 10, "mhpmevent13"}, 374 {MISCREG_MHPMEVENT_BASE + 11, "mhpmevent14"}, 375 {MISCREG_MHPMEVENT_BASE + 12, "mhpmevent15"}, 376 {MISCREG_MHPMEVENT_BASE + 13, "mhpmevent16"}, 377 {MISCREG_MHPMEVENT_BASE + 14, "mhpmevent17"}, 378 {MISCREG_MHPMEVENT_BASE + 15, "mhpmevent18"}, 379 {MISCREG_MHPMEVENT_BASE + 16, "mhpmevent19"}, 380 {MISCREG_MHPMEVENT_BASE + 17, "mhpmevent20"}, 381 {MISCREG_MHPMEVENT_BASE + 18, "mhpmevent21"}, 382 {MISCREG_MHPMEVENT_BASE + 19, "mhpmevent22"}, 383 {MISCREG_MHPMEVENT_BASE + 20, "mhpmevent23"}, 384 {MISCREG_MHPMEVENT_BASE + 21, "mhpmevent24"}, 385 {MISCREG_MHPMEVENT_BASE + 22, "mhpmevent25"}, 386 {MISCREG_MHPMEVENT_BASE + 23, "mhpmevent26"}, 387 {MISCREG_MHPMEVENT_BASE + 24, "mhpmevent27"}, 388 {MISCREG_MHPMEVENT_BASE + 25, "mhpmevent28"}, 389 {MISCREG_MHPMEVENT_BASE + 26, "mhpmevent29"}, 390 {MISCREG_MHPMEVENT_BASE + 27, "mhpmevent30"}, 391 {MISCREG_MHPMEVENT_BASE + 28, "mhpmevent31"}, 392 393 {MISCREG_TSELECT, "tselect"}, 394 {MISCREG_TDATA1, "tdata1"}, 395 {MISCREG_TDATA2, "tdata2"}, 396 {MISCREG_TDATA3, "tdata3"}, 397 {MISCREG_DCSR, "dcsr"}, 398 {MISCREG_DPC, "dpc"}, 399 {MISCREG_DSCRATCH, "dscratch"} 400}; 401 402} 403 404#endif // __ARCH_RISCV_REGISTERS_HH__ 405