registers.hh revision 12109:f29e9c5418aa
1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2016 RISC-V Foundation 16 * Copyright (c) 2016 The University of Virginia 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Andreas Hansson 43 * Sven Karlsson 44 * Alec Roelke 45 */ 46 47#ifndef __ARCH_RISCV_REGISTERS_HH__ 48#define __ARCH_RISCV_REGISTERS_HH__ 49 50#include <map> 51#include <string> 52 53#include "arch/generic/types.hh" 54#include "arch/generic/vec_reg.hh" 55#include "arch/isa_traits.hh" 56#include "arch/riscv/generated/max_inst_regs.hh" 57#include "base/types.hh" 58 59namespace RiscvISA { 60 61using RiscvISAInst::MaxInstSrcRegs; 62using RiscvISAInst::MaxInstDestRegs; 63const int MaxMiscDestRegs = 1; 64 65typedef uint64_t IntReg; 66typedef uint64_t FloatRegBits; 67typedef double FloatReg; 68typedef uint8_t CCReg; // Not applicable to Riscv 69typedef uint64_t MiscReg; 70 71// dummy typedefs since we don't have vector regs 72const unsigned NumVecElemPerVecReg = 2; 73using VecElem = uint32_t; 74using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 75using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 76using VecRegContainer = VecReg::Container; 77 78const int NumIntArchRegs = 32; 79const int NumMicroIntRegs = 1; 80const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs; 81const int NumFloatRegs = 32; 82// This has to be one to prevent warnings that are treated as errors 83const unsigned NumVecRegs = 1; 84const int NumCCRegs = 0; 85const int NumMiscRegs = 4096; 86 87// Semantically meaningful register indices 88const int ZeroReg = 0; 89const int ReturnAddrReg = 1; 90const int StackPointerReg = 2; 91const int GlobalPointerReg = 3; 92const int ThreadPointerReg = 4; 93const int FramePointerReg = 8; 94const int ReturnValueRegs[] = {10, 11}; 95const int ReturnValueReg = ReturnValueRegs[0]; 96const int ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17}; 97const int AMOTempReg = 32; 98 99const char* const RegisterNames[] = {"zero", "ra", "sp", "gp", 100 "tp", "t0", "t1", "t2", 101 "s0", "s1", "a0", "a1", 102 "a2", "a3", "a4", "a5", 103 "a6", "a7", "s2", "s3", 104 "s4", "s5", "s6", "s7", 105 "s8", "s9", "s10", "s11", 106 "t3", "t4", "t5", "t6"}; 107 108const int SyscallNumReg = ArgumentRegs[7]; 109const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1], 110 ArgumentRegs[2], ArgumentRegs[3]}; 111const int SyscallPseudoReturnReg = ReturnValueRegs[0]; 112 113const int NumHpmcounter = 29; 114const int NumHpmcounterh = 29; 115const int NumMhpmcounter = 29; 116const int NumMhpmevent = 29; 117enum MiscRegIndex { 118 MISCREG_USTATUS = 0x000, 119 MISCREG_UIE = 0x004, 120 MISCREG_UTVEC = 0x005, 121 MISCREG_USCRATCH = 0x040, 122 MISCREG_UEPC = 0x041, 123 MISCREG_UCAUSE = 0x042, 124 MISCREG_UBADADDR = 0x043, 125 MISCREG_UIP = 0x044, 126 MISCREG_FFLAGS = 0x001, 127 MISCREG_FRM = 0x002, 128 MISCREG_FCSR = 0x003, 129 MISCREG_CYCLE = 0xC00, 130 MISCREG_TIME = 0xC01, 131 MISCREG_INSTRET = 0xC02, 132 MISCREG_HPMCOUNTER_BASE = 0xC03, 133 MISCREG_CYCLEH = 0xC80, 134 MISCREG_TIMEH = 0xC81, 135 MISCREG_INSTRETH = 0xC82, 136 MISCREG_HPMCOUNTERH_BASE = 0xC83, 137 138 MISCREG_SSTATUS = 0x100, 139 MISCREG_SEDELEG = 0x102, 140 MISCREG_SIDELEG = 0x103, 141 MISCREG_SIE = 0x104, 142 MISCREG_STVEC = 0x105, 143 MISCREG_SSCRATCH = 0x140, 144 MISCREG_SEPC = 0x141, 145 MISCREG_SCAUSE = 0x142, 146 MISCREG_SBADADDR = 0x143, 147 MISCREG_SIP = 0x144, 148 MISCREG_SPTBR = 0x180, 149 150 MISCREG_HSTATUS = 0x200, 151 MISCREG_HEDELEG = 0x202, 152 MISCREG_HIDELEG = 0x203, 153 MISCREG_HIE = 0x204, 154 MISCREG_HTVEC = 0x205, 155 MISCREG_HSCRATCH = 0x240, 156 MISCREG_HEPC = 0x241, 157 MISCREG_HCAUSE = 0x242, 158 MISCREG_HBADADDR = 0x243, 159 MISCREG_HIP = 0x244, 160 161 MISCREG_MVENDORID = 0xF11, 162 MISCREG_MARCHID = 0xF12, 163 MISCREG_MIMPID = 0xF13, 164 MISCREG_MHARTID = 0xF14, 165 MISCREG_MSTATUS = 0x300, 166 MISCREG_MISA = 0x301, 167 MISCREG_MEDELEG = 0x302, 168 MISCREG_MIDELEG = 0x303, 169 MISCREG_MIE = 0x304, 170 MISCREG_MTVEC = 0x305, 171 MISCREG_MSCRATCH = 0x340, 172 MISCREG_MEPC = 0x341, 173 MISCREG_MCAUSE = 0x342, 174 MISCREG_MBADADDR = 0x343, 175 MISCREG_MIP = 0x344, 176 MISCREG_MBASE = 0x380, 177 MISCREG_MBOUND = 0x381, 178 MISCREG_MIBASE = 0x382, 179 MISCREG_MIBOUND = 0x383, 180 MISCREG_MDBASE = 0x384, 181 MISCREG_MDBOUND = 0x385, 182 MISCREG_MCYCLE = 0xB00, 183 MISCREG_MINSTRET = 0xB02, 184 MISCREG_MHPMCOUNTER_BASE = 0xB03, 185 MISCREG_MUCOUNTEREN = 0x320, 186 MISCREG_MSCOUNTEREN = 0x321, 187 MISCREG_MHCOUNTEREN = 0x322, 188 MISCREG_MHPMEVENT_BASE = 0x323, 189 190 MISCREG_TSELECT = 0x7A0, 191 MISCREG_TDATA1 = 0x7A1, 192 MISCREG_TDATA2 = 0x7A2, 193 MISCREG_TDATA3 = 0x7A3, 194 MISCREG_DCSR = 0x7B0, 195 MISCREG_DPC = 0x7B1, 196 MISCREG_DSCRATCH = 0x7B2 197}; 198 199} 200 201#endif // __ARCH_RISCV_REGISTERS_HH__ 202