registers.hh revision 12104:edd63f9c6184
1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2016 RISC-V Foundation 16 * Copyright (c) 2016 The University of Virginia 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Andreas Hansson 43 * Sven Karlsson 44 * Alec Roelke 45 */ 46 47#ifndef __ARCH_RISCV_REGISTERS_HH__ 48#define __ARCH_RISCV_REGISTERS_HH__ 49 50#include <map> 51#include <string> 52 53#include "arch/generic/types.hh" 54#include "arch/isa_traits.hh" 55#include "arch/riscv/generated/max_inst_regs.hh" 56#include "base/types.hh" 57 58namespace RiscvISA { 59 60using RiscvISAInst::MaxInstSrcRegs; 61using RiscvISAInst::MaxInstDestRegs; 62const int MaxMiscDestRegs = 1; 63 64typedef uint64_t IntReg; 65typedef uint64_t FloatRegBits; 66typedef double FloatReg; 67typedef uint8_t CCReg; // Not applicable to Riscv 68typedef uint64_t MiscReg; 69 70const int NumIntArchRegs = 32; 71const int NumMicroIntRegs = 1; 72const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs; 73const int NumFloatRegs = 32; 74const int NumCCRegs = 0; 75const int NumMiscRegs = 4096; 76 77// Semantically meaningful register indices 78const int ZeroReg = 0; 79const int ReturnAddrReg = 1; 80const int StackPointerReg = 2; 81const int GlobalPointerReg = 3; 82const int ThreadPointerReg = 4; 83const int FramePointerReg = 8; 84const int ReturnValueRegs[] = {10, 11}; 85const int ReturnValueReg = ReturnValueRegs[0]; 86const int ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17}; 87const int AMOTempReg = 32; 88 89const char* const RegisterNames[] = {"zero", "ra", "sp", "gp", 90 "tp", "t0", "t1", "t2", 91 "s0", "s1", "a0", "a1", 92 "a2", "a3", "a4", "a5", 93 "a6", "a7", "s2", "s3", 94 "s4", "s5", "s6", "s7", 95 "s8", "s9", "s10", "s11", 96 "t3", "t4", "t5", "t6"}; 97 98const int SyscallNumReg = ArgumentRegs[7]; 99const int SyscallArgumentRegs[] = {ArgumentRegs[0], ArgumentRegs[1], 100 ArgumentRegs[2], ArgumentRegs[3]}; 101const int SyscallPseudoReturnReg = ReturnValueRegs[0]; 102 103const int NumHpmcounter = 29; 104const int NumHpmcounterh = 29; 105const int NumMhpmcounter = 29; 106const int NumMhpmevent = 29; 107enum MiscRegIndex { 108 MISCREG_USTATUS = 0x000, 109 MISCREG_UIE = 0x004, 110 MISCREG_UTVEC = 0x005, 111 MISCREG_USCRATCH = 0x040, 112 MISCREG_UEPC = 0x041, 113 MISCREG_UCAUSE = 0x042, 114 MISCREG_UBADADDR = 0x043, 115 MISCREG_UIP = 0x044, 116 MISCREG_FFLAGS = 0x001, 117 MISCREG_FRM = 0x002, 118 MISCREG_FCSR = 0x003, 119 MISCREG_CYCLE = 0xC00, 120 MISCREG_TIME = 0xC01, 121 MISCREG_INSTRET = 0xC02, 122 MISCREG_HPMCOUNTER_BASE = 0xC03, 123 MISCREG_CYCLEH = 0xC80, 124 MISCREG_TIMEH = 0xC81, 125 MISCREG_INSTRETH = 0xC82, 126 MISCREG_HPMCOUNTERH_BASE = 0xC83, 127 128 MISCREG_SSTATUS = 0x100, 129 MISCREG_SEDELEG = 0x102, 130 MISCREG_SIDELEG = 0x103, 131 MISCREG_SIE = 0x104, 132 MISCREG_STVEC = 0x105, 133 MISCREG_SSCRATCH = 0x140, 134 MISCREG_SEPC = 0x141, 135 MISCREG_SCAUSE = 0x142, 136 MISCREG_SBADADDR = 0x143, 137 MISCREG_SIP = 0x144, 138 MISCREG_SPTBR = 0x180, 139 140 MISCREG_HSTATUS = 0x200, 141 MISCREG_HEDELEG = 0x202, 142 MISCREG_HIDELEG = 0x203, 143 MISCREG_HIE = 0x204, 144 MISCREG_HTVEC = 0x205, 145 MISCREG_HSCRATCH = 0x240, 146 MISCREG_HEPC = 0x241, 147 MISCREG_HCAUSE = 0x242, 148 MISCREG_HBADADDR = 0x243, 149 MISCREG_HIP = 0x244, 150 151 MISCREG_MVENDORID = 0xF11, 152 MISCREG_MARCHID = 0xF12, 153 MISCREG_MIMPID = 0xF13, 154 MISCREG_MHARTID = 0xF14, 155 MISCREG_MSTATUS = 0x300, 156 MISCREG_MISA = 0x301, 157 MISCREG_MEDELEG = 0x302, 158 MISCREG_MIDELEG = 0x303, 159 MISCREG_MIE = 0x304, 160 MISCREG_MTVEC = 0x305, 161 MISCREG_MSCRATCH = 0x340, 162 MISCREG_MEPC = 0x341, 163 MISCREG_MCAUSE = 0x342, 164 MISCREG_MBADADDR = 0x343, 165 MISCREG_MIP = 0x344, 166 MISCREG_MBASE = 0x380, 167 MISCREG_MBOUND = 0x381, 168 MISCREG_MIBASE = 0x382, 169 MISCREG_MIBOUND = 0x383, 170 MISCREG_MDBASE = 0x384, 171 MISCREG_MDBOUND = 0x385, 172 MISCREG_MCYCLE = 0xB00, 173 MISCREG_MINSTRET = 0xB02, 174 MISCREG_MHPMCOUNTER_BASE = 0xB03, 175 MISCREG_MUCOUNTEREN = 0x320, 176 MISCREG_MSCOUNTEREN = 0x321, 177 MISCREG_MHCOUNTEREN = 0x322, 178 MISCREG_MHPMEVENT_BASE = 0x323, 179 180 MISCREG_TSELECT = 0x7A0, 181 MISCREG_TDATA1 = 0x7A1, 182 MISCREG_TDATA2 = 0x7A2, 183 MISCREG_TDATA3 = 0x7A3, 184 MISCREG_DCSR = 0x7B0, 185 MISCREG_DPC = 0x7B1, 186 MISCREG_DSCRATCH = 0x7B2 187}; 188 189} 190 191#endif // __ARCH_RISCV_REGISTERS_HH__ 192