process.cc revision 12431 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Ali Saidi
31 *          Korey Sewell
32 *          Alec Roelke
33 */
34#include "arch/riscv/process.hh"
35
36#include <algorithm>
37#include <cstddef>
38#include <iostream>
39#include <iterator>
40#include <map>
41#include <string>
42#include <vector>
43
44#include "arch/riscv/isa_traits.hh"
45#include "base/loader/elf_object.hh"
46#include "base/loader/object_file.hh"
47#include "base/logging.hh"
48#include "base/random.hh"
49#include "cpu/thread_context.hh"
50#include "debug/Stack.hh"
51#include "mem/page_table.hh"
52#include "params/Process.hh"
53#include "sim/aux_vector.hh"
54#include "sim/process.hh"
55#include "sim/process_impl.hh"
56#include "sim/syscall_return.hh"
57#include "sim/system.hh"
58
59using namespace std;
60using namespace RiscvISA;
61
62RiscvProcess::RiscvProcess(ProcessParams *params, ObjectFile *objFile) :
63        Process(params, new FuncPageTable(params->name, params->pid), objFile)
64{
65    fatal_if(!params->useArchPT, "Arch page tables not implemented.");
66    const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
67    const Addr max_stack_size = 8 * 1024 * 1024;
68    const Addr next_thread_stack_base = stack_base - max_stack_size;
69    const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
70            PageBytes);
71    const Addr mmap_end = 0x4000000000000000L;
72    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
73            next_thread_stack_base, mmap_end);
74}
75
76void
77RiscvProcess::initState()
78{
79    Process::initState();
80
81    argsInit<uint64_t>(PageBytes);
82}
83
84template<class IntType> void
85RiscvProcess::argsInit(int pageSize)
86{
87    const int RandomBytes = 16;
88
89    updateBias();
90    objFile->loadSections(initVirtMem);
91    ElfObject* elfObject = dynamic_cast<ElfObject*>(objFile);
92    memState->setStackMin(memState->getStackBase());
93
94    // Determine stack size and populate auxv
95    Addr stack_top = memState->getStackMin();
96    stack_top -= RandomBytes;
97    for (const string& arg: argv)
98        stack_top -= arg.size() + 1;
99    for (const string& env: envp)
100        stack_top -= env.size() + 1;
101    stack_top &= -sizeof(Addr);
102
103    vector<AuxVector<IntType>> auxv;
104    if (elfObject != nullptr) {
105        auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()});
106        auxv.push_back({M5_AT_PHNUM, elfObject->programHeaderCount()});
107        auxv.push_back({M5_AT_PHENT, elfObject->programHeaderSize()});
108        auxv.push_back({M5_AT_PHDR, elfObject->programHeaderTable()});
109        auxv.push_back({M5_AT_PAGESZ, PageBytes});
110        auxv.push_back({M5_AT_SECURE, 0});
111        auxv.push_back({M5_AT_RANDOM, stack_top});
112        auxv.push_back({M5_AT_NULL, 0});
113    }
114    stack_top -= (1 + argv.size()) * sizeof(Addr) +
115                   (1 + envp.size()) * sizeof(Addr) +
116                   sizeof(Addr) + 2 * sizeof(IntType) * auxv.size();
117    stack_top &= -2*sizeof(Addr);
118    memState->setStackSize(memState->getStackBase() - stack_top);
119    allocateMem(roundDown(stack_top, pageSize),
120            roundUp(memState->getStackSize(), pageSize));
121
122    // Copy random bytes (for AT_RANDOM) to stack
123    memState->setStackMin(memState->getStackMin() - RandomBytes);
124    uint8_t at_random[RandomBytes];
125    generate(begin(at_random), end(at_random),
126             [&]{ return random_mt.random(0, 0xFF); });
127    initVirtMem.writeBlob(memState->getStackMin(), at_random, RandomBytes);
128
129    // Copy argv to stack
130    vector<Addr> argPointers;
131    for (const string& arg: argv) {
132        memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
133        initVirtMem.writeString(memState->getStackMin(), arg.c_str());
134        argPointers.push_back(memState->getStackMin());
135        if (DTRACE(Stack)) {
136            string wrote;
137            initVirtMem.readString(wrote, argPointers.back());
138            DPRINTFN("Wrote arg \"%s\" to address %p\n",
139                    wrote, (void*)memState->getStackMin());
140        }
141    }
142    argPointers.push_back(0);
143
144    // Copy envp to stack
145    vector<Addr> envPointers;
146    for (const string& env: envp) {
147        memState->setStackMin(memState->getStackMin() - (env.size() + 1));
148        initVirtMem.writeString(memState->getStackMin(), env.c_str());
149        envPointers.push_back(memState->getStackMin());
150        DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
151                env, (void*)memState->getStackMin());
152    }
153    envPointers.push_back(0);
154
155    // Align stack
156    memState->setStackMin(memState->getStackMin() & -sizeof(Addr));
157
158    // Calculate bottom of stack
159    memState->setStackMin(memState->getStackMin() -
160            ((1 + argv.size()) * sizeof(Addr) +
161             (1 + envp.size()) * sizeof(Addr) +
162             sizeof(Addr) + 2 * sizeof(IntType) * auxv.size()));
163    memState->setStackMin(memState->getStackMin() & -2*sizeof(Addr));
164    Addr sp = memState->getStackMin();
165    const auto pushOntoStack =
166        [this, &sp](const uint8_t* data, const size_t size) {
167            initVirtMem.writeBlob(sp, data, size);
168            sp += size;
169        };
170
171    // Push argc and argv pointers onto stack
172    IntType argc = htog((IntType)argv.size());
173    DPRINTF(Stack, "Wrote argc %d to address %p\n",
174            argv.size(), (void*)sp);
175    pushOntoStack((uint8_t*)&argc, sizeof(IntType));
176    for (const Addr& argPointer: argPointers) {
177        DPRINTF(Stack, "Wrote argv pointer %p to address %p\n",
178                (void*)argPointer, (void*)sp);
179        pushOntoStack((uint8_t*)&argPointer, sizeof(Addr));
180    }
181
182    // Push env pointers onto stack
183    for (const Addr& envPointer: envPointers) {
184        DPRINTF(Stack, "Wrote envp pointer %p to address %p\n",
185                (void*)envPointer, (void*)sp);
186        pushOntoStack((uint8_t*)&envPointer, sizeof(Addr));
187    }
188
189    // Push aux vector onto stack
190    std::map<IntType, string> aux_keys = {
191        {M5_AT_ENTRY, "M5_AT_ENTRY"},
192        {M5_AT_PHNUM, "M5_AT_PHNUM"},
193        {M5_AT_PHENT, "M5_AT_PHENT"},
194        {M5_AT_PHDR, "M5_AT_PHDR"},
195        {M5_AT_PAGESZ, "M5_AT_PAGESZ"},
196        {M5_AT_SECURE, "M5_AT_SECURE"},
197        {M5_AT_RANDOM, "M5_AT_RANDOM"},
198        {M5_AT_NULL, "M5_AT_NULL"}
199    };
200    for (const AuxVector<IntType>& aux: auxv) {
201        DPRINTF(Stack, "Wrote aux key %s to address %p\n",
202                aux_keys[aux.a_type], (void*)sp);
203        pushOntoStack((uint8_t*)&aux.a_type, sizeof(IntType));
204        DPRINTF(Stack, "Wrote aux value %x to address %p\n",
205                aux.a_val, (void*)sp);
206        pushOntoStack((uint8_t*)&aux.a_val, sizeof(IntType));
207    }
208
209    ThreadContext *tc = system->getThreadContext(contextIds[0]);
210    tc->setIntReg(StackPointerReg, memState->getStackMin());
211    tc->pcState(getStartPC());
212
213    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
214}
215
216RiscvISA::IntReg
217RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
218{
219    // If a larger index is requested than there are syscall argument
220    // registers, return 0
221    RiscvISA::IntReg retval = 0;
222    if (i < SyscallArgumentRegs.size())
223        retval = tc->readIntReg(SyscallArgumentRegs[i]);
224    i++;
225    return retval;
226}
227
228void
229RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val)
230{
231    tc->setIntReg(SyscallArgumentRegs[i], val);
232}
233
234void
235RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
236{
237    if (sysret.successful()) {
238        // no error
239        tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue());
240    } else {
241        // got an error, return details
242        tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue());
243    }
244}
245