process.cc revision 11851
112641Sgiacomo.travaglini@arm.com/* 212641Sgiacomo.travaglini@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 312641Sgiacomo.travaglini@arm.com * Copyright (c) 2016 The University of Virginia 412641Sgiacomo.travaglini@arm.com * All rights reserved. 512641Sgiacomo.travaglini@arm.com * 612641Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 712641Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 812641Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 912641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1012641Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1112641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1212641Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1312641Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1412641Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1512641Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 1612641Sgiacomo.travaglini@arm.com * 1712641Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812641Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912641Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012641Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112641Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212641Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312641Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412641Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512641Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612641Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2712641Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2812641Sgiacomo.travaglini@arm.com * 2912641Sgiacomo.travaglini@arm.com * Authors: Gabe Black 3012641Sgiacomo.travaglini@arm.com * Ali Saidi 3112641Sgiacomo.travaglini@arm.com * Korey Sewell 3212641Sgiacomo.travaglini@arm.com * Alec Roelke 3312641Sgiacomo.travaglini@arm.com */ 3412641Sgiacomo.travaglini@arm.com#include "arch/riscv/process.hh" 3512641Sgiacomo.travaglini@arm.com 3612641Sgiacomo.travaglini@arm.com#include <vector> 3712641Sgiacomo.travaglini@arm.com 3812641Sgiacomo.travaglini@arm.com#include "arch/riscv/isa_traits.hh" 3912641Sgiacomo.travaglini@arm.com#include "base/loader/elf_object.hh" 4012641Sgiacomo.travaglini@arm.com#include "base/loader/object_file.hh" 4112641Sgiacomo.travaglini@arm.com#include "base/misc.hh" 4212641Sgiacomo.travaglini@arm.com#include "cpu/thread_context.hh" 4312641Sgiacomo.travaglini@arm.com#include "debug/Loader.hh" 4412641Sgiacomo.travaglini@arm.com#include "mem/page_table.hh" 4512641Sgiacomo.travaglini@arm.com#include "sim/process.hh" 4612641Sgiacomo.travaglini@arm.com#include "sim/process_impl.hh" 4712641Sgiacomo.travaglini@arm.com#include "sim/syscall_return.hh" 4812641Sgiacomo.travaglini@arm.com#include "sim/system.hh" 4912641Sgiacomo.travaglini@arm.com 5012641Sgiacomo.travaglini@arm.comusing namespace std; 5112641Sgiacomo.travaglini@arm.comusing namespace RiscvISA; 5212641Sgiacomo.travaglini@arm.com 5312641Sgiacomo.travaglini@arm.comRiscvProcess::RiscvProcess(ProcessParams * params, 5412641Sgiacomo.travaglini@arm.com ObjectFile *objFile) : Process(params, objFile) 5512641Sgiacomo.travaglini@arm.com{ 5612641Sgiacomo.travaglini@arm.com // Set up stack. On RISC-V, stack starts at the top of kuseg 5712641Sgiacomo.travaglini@arm.com // user address space. RISC-V stack grows down from here 5812641Sgiacomo.travaglini@arm.com stack_base = 0x7FFFFFFF; 5912641Sgiacomo.travaglini@arm.com 6012641Sgiacomo.travaglini@arm.com // Set pointer for next thread stack. Reserve 8M for main stack. 6112641Sgiacomo.travaglini@arm.com next_thread_stack_base = stack_base - (8 * 1024 * 1024); 6212641Sgiacomo.travaglini@arm.com 6312641Sgiacomo.travaglini@arm.com // Set up break point (Top of Heap) 6412641Sgiacomo.travaglini@arm.com brk_point = objFile->bssBase() + objFile->bssSize(); 6512641Sgiacomo.travaglini@arm.com 6612641Sgiacomo.travaglini@arm.com // Set up region for mmaps. Start it 1GB above the top of the heap. 6712641Sgiacomo.travaglini@arm.com mmap_end = brk_point + 0x40000000L; 6812641Sgiacomo.travaglini@arm.com} 6912641Sgiacomo.travaglini@arm.com 7012641Sgiacomo.travaglini@arm.comvoid 7112641Sgiacomo.travaglini@arm.comRiscvProcess::initState() 7212641Sgiacomo.travaglini@arm.com{ 7312641Sgiacomo.travaglini@arm.com Process::initState(); 7412641Sgiacomo.travaglini@arm.com 7512641Sgiacomo.travaglini@arm.com argsInit<uint64_t>(PageBytes); 7612641Sgiacomo.travaglini@arm.com} 7712641Sgiacomo.travaglini@arm.com 7812641Sgiacomo.travaglini@arm.comtemplate<class IntType> void 7912641Sgiacomo.travaglini@arm.comRiscvProcess::argsInit(int pageSize) 8012641Sgiacomo.travaglini@arm.com{ 8112641Sgiacomo.travaglini@arm.com updateBias(); 8212641Sgiacomo.travaglini@arm.com 8312641Sgiacomo.travaglini@arm.com // load object file into target memory 8412641Sgiacomo.travaglini@arm.com objFile->loadSections(initVirtMem); 8512641Sgiacomo.travaglini@arm.com 8612641Sgiacomo.travaglini@arm.com typedef AuxVector<IntType> auxv_t; 8712641Sgiacomo.travaglini@arm.com vector<auxv_t> auxv; 8812641Sgiacomo.travaglini@arm.com ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 8912641Sgiacomo.travaglini@arm.com if (elfObject) { 9012641Sgiacomo.travaglini@arm.com // Set the system page size 9112641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes)); 9212641Sgiacomo.travaglini@arm.com // Set the frequency at which time() increments 9312641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 9412641Sgiacomo.travaglini@arm.com // For statically linked executables, this is the virtual 9512641Sgiacomo.travaglini@arm.com // address of the program header tables if they appear in the 9612641Sgiacomo.travaglini@arm.com // executable image. 9712641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 9812641Sgiacomo.travaglini@arm.com DPRINTF(Loader, "auxv at PHDR %08p\n", 9912641Sgiacomo.travaglini@arm.com elfObject->programHeaderTable()); 10012641Sgiacomo.travaglini@arm.com // This is the size of a program header entry from the elf file. 10112641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 10212641Sgiacomo.travaglini@arm.com // This is the number of program headers from the original elf file. 10312641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 10412641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 10512641Sgiacomo.travaglini@arm.com //The entry point to the program 10612641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 10712641Sgiacomo.travaglini@arm.com //Different user and group IDs 10812641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_UID, uid())); 10912641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_EUID, euid())); 11012641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_GID, gid())); 11112641Sgiacomo.travaglini@arm.com auxv.push_back(auxv_t(M5_AT_EGID, egid())); 11212641Sgiacomo.travaglini@arm.com } 11312641Sgiacomo.travaglini@arm.com 11412641Sgiacomo.travaglini@arm.com const IntType zero = 0; 11512641Sgiacomo.travaglini@arm.com IntType argc = htog((IntType)argv.size()); 11612641Sgiacomo.travaglini@arm.com int argv_array_size = sizeof(Addr) * argv.size(); 11712641Sgiacomo.travaglini@arm.com int arg_data_size = 0; 11812641Sgiacomo.travaglini@arm.com for (string arg: argv) 11912641Sgiacomo.travaglini@arm.com arg_data_size += arg.size() + 1; 12012641Sgiacomo.travaglini@arm.com int envp_array_size = sizeof(Addr) * envp.size(); 12112641Sgiacomo.travaglini@arm.com int env_data_size = 0; 12212641Sgiacomo.travaglini@arm.com for (string env: envp) 12312641Sgiacomo.travaglini@arm.com env_data_size += env.size() + 1; 12412641Sgiacomo.travaglini@arm.com int auxv_array_size = 2 * sizeof(IntType)*auxv.size(); 12512641Sgiacomo.travaglini@arm.com 12612641Sgiacomo.travaglini@arm.com stack_size = sizeof(IntType) + argv_array_size + 2 * sizeof(Addr) + 12712641Sgiacomo.travaglini@arm.com arg_data_size + 2 * sizeof(Addr); 12812641Sgiacomo.travaglini@arm.com if (!envp.empty()) { 12912641Sgiacomo.travaglini@arm.com stack_size += 2 * sizeof(Addr) + envp_array_size + 2 * sizeof(Addr) + 13012641Sgiacomo.travaglini@arm.com env_data_size; 13112641Sgiacomo.travaglini@arm.com } 13212641Sgiacomo.travaglini@arm.com if (!auxv.empty()) 13312641Sgiacomo.travaglini@arm.com stack_size += 2 * sizeof(Addr) + auxv_array_size; 13412641Sgiacomo.travaglini@arm.com stack_min = roundDown(stack_base - stack_size, pageSize); 13512641Sgiacomo.travaglini@arm.com allocateMem(stack_min, roundUp(stack_size, pageSize)); 13612641Sgiacomo.travaglini@arm.com 13712641Sgiacomo.travaglini@arm.com Addr argv_array_base = stack_min + sizeof(IntType); 13812641Sgiacomo.travaglini@arm.com Addr arg_data_base = argv_array_base + argv_array_size + 2 * sizeof(Addr); 13912641Sgiacomo.travaglini@arm.com Addr envp_array_base = arg_data_base + arg_data_size; 14012641Sgiacomo.travaglini@arm.com if (!envp.empty()) 14112641Sgiacomo.travaglini@arm.com envp_array_base += 2 * sizeof(Addr); 14212641Sgiacomo.travaglini@arm.com Addr env_data_base = envp_array_base + envp_array_size; 14312641Sgiacomo.travaglini@arm.com if (!envp.empty()) 14412641Sgiacomo.travaglini@arm.com env_data_base += 2 * sizeof(Addr); 14512641Sgiacomo.travaglini@arm.com 14612641Sgiacomo.travaglini@arm.com vector<Addr> arg_pointers; 14712641Sgiacomo.travaglini@arm.com if (!argv.empty()) { 14812641Sgiacomo.travaglini@arm.com arg_pointers.push_back(arg_data_base); 14912641Sgiacomo.travaglini@arm.com for (int i = 0; i < argv.size() - 1; i++) { 15012641Sgiacomo.travaglini@arm.com arg_pointers.push_back(arg_pointers[i] + argv[i].size() + 1); 15112641Sgiacomo.travaglini@arm.com } 15212641Sgiacomo.travaglini@arm.com } 15312641Sgiacomo.travaglini@arm.com 15412641Sgiacomo.travaglini@arm.com vector<Addr> env_pointers; 15512641Sgiacomo.travaglini@arm.com if (!envp.empty()) { 15612641Sgiacomo.travaglini@arm.com env_pointers.push_back(env_data_base); 15712641Sgiacomo.travaglini@arm.com for (int i = 0; i < envp.size() - 1; i++) { 15812641Sgiacomo.travaglini@arm.com env_pointers.push_back(env_pointers[i] + envp[i].size() + 1); 15912641Sgiacomo.travaglini@arm.com } 16012641Sgiacomo.travaglini@arm.com } 16112641Sgiacomo.travaglini@arm.com 16212641Sgiacomo.travaglini@arm.com Addr sp = stack_min; 16312641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp, (uint8_t *)&argc, sizeof(IntType)); 16412641Sgiacomo.travaglini@arm.com sp += sizeof(IntType); 16512641Sgiacomo.travaglini@arm.com for (Addr arg_pointer: arg_pointers) { 16612641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp, (uint8_t *)&arg_pointer, sizeof(Addr)); 16712641Sgiacomo.travaglini@arm.com sp += sizeof(Addr); 16812641Sgiacomo.travaglini@arm.com } 16912641Sgiacomo.travaglini@arm.com for (int i = 0; i < 2; i++) { 17012641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 17112641Sgiacomo.travaglini@arm.com sp += sizeof(Addr); 17212641Sgiacomo.travaglini@arm.com } 17312641Sgiacomo.travaglini@arm.com for (int i = 0; i < argv.size(); i++) { 17412641Sgiacomo.travaglini@arm.com initVirtMem.writeString(sp, argv[i].c_str()); 17512641Sgiacomo.travaglini@arm.com sp += argv[i].size() + 1; 17612641Sgiacomo.travaglini@arm.com } 17712641Sgiacomo.travaglini@arm.com if (!envp.empty()) { 17812641Sgiacomo.travaglini@arm.com for (int i = 0; i < 2; i++) { 17912641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 18012641Sgiacomo.travaglini@arm.com sp += sizeof(Addr); 18112641Sgiacomo.travaglini@arm.com } 18212641Sgiacomo.travaglini@arm.com } 18312641Sgiacomo.travaglini@arm.com for (Addr env_pointer: env_pointers) 18412641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp, (uint8_t *)&env_pointer, sizeof(Addr)); 18512641Sgiacomo.travaglini@arm.com if (!envp.empty()) { 18612641Sgiacomo.travaglini@arm.com for (int i = 0; i < 2; i++) { 18712641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 18812641Sgiacomo.travaglini@arm.com sp += sizeof(Addr); 18912641Sgiacomo.travaglini@arm.com } 19012641Sgiacomo.travaglini@arm.com } 19112641Sgiacomo.travaglini@arm.com for (int i = 0; i < envp.size(); i++) { 19212641Sgiacomo.travaglini@arm.com initVirtMem.writeString(sp, envp[i].c_str()); 19312641Sgiacomo.travaglini@arm.com sp += envp[i].size() + 1; 19412641Sgiacomo.travaglini@arm.com } 19512641Sgiacomo.travaglini@arm.com if (!auxv.empty()) { 19612641Sgiacomo.travaglini@arm.com for (int i = 0; i < 2; i++) { 19712641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 19812641Sgiacomo.travaglini@arm.com sp += sizeof(Addr); 19912641Sgiacomo.travaglini@arm.com } 20012641Sgiacomo.travaglini@arm.com } 20112641Sgiacomo.travaglini@arm.com for (auxv_t aux: auxv) { 20212641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp, (uint8_t *)&aux.a_type, sizeof(IntType)); 20312641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp + sizeof(IntType), (uint8_t *)&aux.a_val, 20412641Sgiacomo.travaglini@arm.com sizeof(IntType)); 20512641Sgiacomo.travaglini@arm.com sp += 2 * sizeof(IntType); 20612641Sgiacomo.travaglini@arm.com } 20712641Sgiacomo.travaglini@arm.com for (int i = 0; i < 2; i++) { 20812641Sgiacomo.travaglini@arm.com initVirtMem.writeBlob(sp, (uint8_t *)&zero, sizeof(Addr)); 20912641Sgiacomo.travaglini@arm.com sp += sizeof(Addr); 21012641Sgiacomo.travaglini@arm.com } 21112641Sgiacomo.travaglini@arm.com 21212641Sgiacomo.travaglini@arm.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 21312641Sgiacomo.travaglini@arm.com tc->setIntReg(StackPointerReg, stack_min); 21412641Sgiacomo.travaglini@arm.com tc->pcState(getStartPC()); 21512641Sgiacomo.travaglini@arm.com} 21612641Sgiacomo.travaglini@arm.com 21712641Sgiacomo.travaglini@arm.comRiscvISA::IntReg 21812641Sgiacomo.travaglini@arm.comRiscvProcess::getSyscallArg(ThreadContext *tc, int &i) 21912641Sgiacomo.travaglini@arm.com{ 22012641Sgiacomo.travaglini@arm.com // RISC-V only has four system call argument registers by convention, so 22112641Sgiacomo.travaglini@arm.com // if a larger index is requested return 0 22212641Sgiacomo.travaglini@arm.com RiscvISA::IntReg retval = 0; 22312641Sgiacomo.travaglini@arm.com if (i < 4) 22412641Sgiacomo.travaglini@arm.com retval = tc->readIntReg(SyscallArgumentRegs[i]); 22512641Sgiacomo.travaglini@arm.com i++; 22612641Sgiacomo.travaglini@arm.com return retval; 22712641Sgiacomo.travaglini@arm.com} 22812641Sgiacomo.travaglini@arm.com 22912641Sgiacomo.travaglini@arm.comvoid 23012641Sgiacomo.travaglini@arm.comRiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val) 23112641Sgiacomo.travaglini@arm.com{ 23212641Sgiacomo.travaglini@arm.com tc->setIntReg(SyscallArgumentRegs[i], val); 23312641Sgiacomo.travaglini@arm.com} 23412641Sgiacomo.travaglini@arm.com 23512641Sgiacomo.travaglini@arm.comvoid 23612641Sgiacomo.travaglini@arm.comRiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 23712641Sgiacomo.travaglini@arm.com{ 23812641Sgiacomo.travaglini@arm.com if (sysret.successful()) { 23912641Sgiacomo.travaglini@arm.com // no error 24012641Sgiacomo.travaglini@arm.com tc->setIntReg(SyscallPseudoReturnReg, sysret.returnValue()); 24112641Sgiacomo.travaglini@arm.com } else { 24212641Sgiacomo.travaglini@arm.com // got an error, return details 24312641Sgiacomo.travaglini@arm.com tc->setIntReg(SyscallPseudoReturnReg, sysret.errnoValue()); 24412641Sgiacomo.travaglini@arm.com } 24512641Sgiacomo.travaglini@arm.com} 24612641Sgiacomo.travaglini@arm.com