mem.isa revision 12385:288c62455dde
1// -*- mode:c++ -*- 2 3// Copyright (c) 2015 RISC-V Foundation 4// Copyright (c) 2016 The University of Virginia 5// All rights reserved. 6// 7// Redistribution and use in source and binary forms, with or without 8// modification, are permitted provided that the following conditions are 9// met: redistributions of source code must retain the above copyright 10// notice, this list of conditions and the following disclaimer; 11// redistributions in binary form must reproduce the above copyright 12// notice, this list of conditions and the following disclaimer in the 13// documentation and/or other materials provided with the distribution; 14// neither the name of the copyright holders nor the names of its 15// contributors may be used to endorse or promote products derived from 16// this software without specific prior written permission. 17// 18// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29// 30// Authors: Alec Roelke 31 32//////////////////////////////////////////////////////////////////// 33// 34// Memory operation instructions 35// 36def template LoadStoreDeclare {{ 37 /** 38 * Static instruction class for "%(mnemonic)s". 39 */ 40 class %(class_name)s : public %(base_class)s 41 { 42 public: 43 /// Constructor. 44 %(class_name)s(ExtMachInst machInst); 45 46 Fault execute(ExecContext *, Trace::InstRecord *) const; 47 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 48 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 49 }; 50}}; 51 52 53def template LoadStoreConstructor {{ 54 %(class_name)s::%(class_name)s(ExtMachInst machInst): 55 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 56 { 57 %(constructor)s; 58 %(offset_code)s; 59 } 60}}; 61 62let {{ 63def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, 64 inst_flags, base_class, postacc_code='', decode_template=BasicDecode, 65 exec_template_base=''): 66 # Make sure flags are in lists (convert to lists if not). 67 mem_flags = makeList(mem_flags) 68 inst_flags = makeList(inst_flags) 69 70 iop = InstObjParams(name, Name, base_class, 71 {'offset_code': offset_code, 'ea_code': ea_code, 72 'memacc_code': memacc_code, 'postacc_code': postacc_code }, 73 inst_flags) 74 75 if mem_flags: 76 mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] 77 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 78 iop.constructor += s 79 80 # select templates 81 82 fullExecTemplate = eval(exec_template_base + 'Execute') 83 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 84 completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 85 86 # (header_output, decoder_output, decode_block, exec_output) 87 return (LoadStoreDeclare.subst(iop), 88 LoadStoreConstructor.subst(iop), 89 decode_template.subst(iop), 90 fullExecTemplate.subst(iop) + 91 initiateAccTemplate.subst(iop) + 92 completeAccTemplate.subst(iop)) 93}}; 94 95def template LoadExecute {{ 96 Fault 97 %(class_name)s::execute( 98 ExecContext *xc, Trace::InstRecord *traceData) const 99 { 100 Addr EA; 101 Fault fault = NoFault; 102 103 %(op_decl)s; 104 %(op_rd)s; 105 %(ea_code)s; 106 107 if (fault == NoFault) { 108 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 109 %(memacc_code)s; 110 } 111 112 if (fault == NoFault) { 113 %(op_wb)s; 114 } 115 116 return fault; 117 } 118}}; 119 120def template LoadInitiateAcc {{ 121 Fault 122 %(class_name)s::initiateAcc(ExecContext *xc, 123 Trace::InstRecord *traceData) const 124 { 125 Addr EA; 126 Fault fault = NoFault; 127 128 %(op_src_decl)s; 129 %(op_rd)s; 130 %(ea_code)s; 131 132 if (fault == NoFault) { 133 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 134 } 135 136 return fault; 137 } 138}}; 139 140def template LoadCompleteAcc {{ 141 Fault 142 %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 143 Trace::InstRecord *traceData) const 144 { 145 Fault fault = NoFault; 146 147 %(op_decl)s; 148 %(op_rd)s; 149 150 getMem(pkt, Mem, traceData); 151 152 if (fault == NoFault) { 153 %(memacc_code)s; 154 } 155 156 if (fault == NoFault) { 157 %(op_wb)s; 158 } 159 160 return fault; 161 } 162}}; 163 164def template StoreExecute {{ 165 Fault 166 %(class_name)s::execute(ExecContext *xc, 167 Trace::InstRecord *traceData) const 168 { 169 Addr EA; 170 Fault fault = NoFault; 171 172 %(op_decl)s; 173 %(op_rd)s; 174 %(ea_code)s; 175 176 if (fault == NoFault) { 177 %(memacc_code)s; 178 } 179 180 if (fault == NoFault) { 181 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 182 nullptr); 183 } 184 185 if (fault == NoFault) { 186 %(postacc_code)s; 187 } 188 189 if (fault == NoFault) { 190 %(op_wb)s; 191 } 192 193 return fault; 194 } 195}}; 196 197def template StoreInitiateAcc {{ 198 Fault 199 %(class_name)s::initiateAcc(ExecContext *xc, 200 Trace::InstRecord *traceData) const 201 { 202 Addr EA; 203 Fault fault = NoFault; 204 205 %(op_decl)s; 206 %(op_rd)s; 207 %(ea_code)s; 208 209 if (fault == NoFault) { 210 %(memacc_code)s; 211 } 212 213 if (fault == NoFault) { 214 fault = writeMemTiming(xc, traceData, Mem, EA, 215 memAccessFlags, nullptr); 216 } 217 218 if (fault == NoFault) { 219 %(op_wb)s; 220 } 221 222 return fault; 223 } 224}}; 225 226def template StoreCompleteAcc {{ 227 Fault 228 %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 229 Trace::InstRecord *traceData) const 230 { 231 return NoFault; 232 } 233}}; 234 235def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}}, 236 offset_code={{offset = sext<12>(IMM12);}}, 237 mem_flags=[], inst_flags=[]) {{ 238 (header_output, decoder_output, decode_block, exec_output) = \ 239 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, 240 inst_flags, 'Load', exec_template_base='Load') 241}}; 242 243def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, 244 offset_code={{offset = sext<12>(IMM5 | (IMM7 << 5));}}, 245 mem_flags=[], inst_flags=[]) {{ 246 (header_output, decoder_output, decode_block, exec_output) = \ 247 LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, 248 inst_flags, 'Store', exec_template_base='Store') 249}}; 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