fp.isa revision 12849:7f43ad13ebf0
16692SN/A// -*- mode:c++ -*- 26692SN/A 36692SN/A// Copyright (c) 2015 Riscv Developers 48835SAli.Saidi@ARM.com// Copyright (c) 2016-2017 The University of Virginia 57935SN/A// All rights reserved. 67935SN/A// 77935SN/A// Redistribution and use in source and binary forms, with or without 86692SN/A// modification, are permitted provided that the following conditions are 96692SN/A// met: redistributions of source code must retain the above copyright 106692SN/A// notice, this list of conditions and the following disclaimer; 119885Sstever@gmail.com// redistributions in binary form must reproduce the above copyright 128835SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer in the 139885Sstever@gmail.com// documentation and/or other materials provided with the distribution; 149885Sstever@gmail.com// neither the name of the copyright holders nor the names of its 158835SAli.Saidi@ARM.com// contributors may be used to endorse or promote products derived from 168835SAli.Saidi@ARM.com// this software without specific prior written permission. 178835SAli.Saidi@ARM.com// 186692SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 199481Snilay@cs.wisc.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 208721SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 218721SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 228835SAli.Saidi@ARM.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 238835SAli.Saidi@ARM.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 247935SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 257935SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 267935SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 277935SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 287935SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 297935SN/A// 307935SN/A// Authors: Alec Roelke 318983Snate@binkert.org 326692SN/A//////////////////////////////////////////////////////////////////// 339885Sstever@gmail.com// 349885Sstever@gmail.com// Floating point operation instructions 359885Sstever@gmail.com// 369885Sstever@gmail.comdef template FloatExecute {{ 379885Sstever@gmail.com Fault %(class_name)s::execute(ExecContext *xc, 386692SN/A Trace::InstRecord *traceData) const 396692SN/A { 409481Snilay@cs.wisc.edu Fault fault = NoFault; 416692SN/A 426692SN/A %(op_decl)s; 439885Sstever@gmail.com %(op_rd)s; 446692SN/A if (fault == NoFault) { 456692SN/A switch (ROUND_MODE) { 468835SAli.Saidi@ARM.com case 0x0: 476692SN/A std::fesetround(FE_TONEAREST); 486692SN/A break; 498983Snate@binkert.org case 0x1: 506692SN/A std::fesetround(FE_TOWARDZERO); 516692SN/A break; 528835SAli.Saidi@ARM.com case 0x2: 539481Snilay@cs.wisc.edu std::fesetround(FE_DOWNWARD); 546692SN/A break; 556692SN/A case 0x3: 566692SN/A std::fesetround(FE_UPWARD); 576692SN/A break; 586692SN/A case 0x4: 596692SN/A // Round to nearest, ties to max magnitude not implemented 608835SAli.Saidi@ARM.com fault = make_shared<IllegalFrmFault>(ROUND_MODE, machInst); 616692SN/A break; 629885Sstever@gmail.com case 0x7: { 639885Sstever@gmail.com uint8_t frm = xc->readMiscReg(MISCREG_FRM); 649885Sstever@gmail.com switch (frm) { 659885Sstever@gmail.com case 0x0: 666692SN/A std::fesetround(FE_TONEAREST); 676692SN/A break; 689481Snilay@cs.wisc.edu case 0x1: 696692SN/A std::fesetround(FE_TOWARDZERO); 706692SN/A break; 716692SN/A case 0x2: 726692SN/A std::fesetround(FE_DOWNWARD); 738983Snate@binkert.org break; 748983Snate@binkert.org case 0x3: 756692SN/A std::fesetround(FE_UPWARD); 766692SN/A break; 776692SN/A case 0x4: 786692SN/A // Round to nearest, ties to max magnitude not implemented 796692SN/A fault = make_shared<IllegalFrmFault>(ROUND_MODE, machInst); 808835SAli.Saidi@ARM.com break; 818835SAli.Saidi@ARM.com default: 828835SAli.Saidi@ARM.com fault = std::make_shared<IllegalFrmFault>(frm, machInst); 839481Snilay@cs.wisc.edu break; 849481Snilay@cs.wisc.edu } 859481Snilay@cs.wisc.edu break; 866692SN/A } 876692SN/A default: 886692SN/A fault = std::make_shared<IllegalFrmFault>(ROUND_MODE, 896692SN/A machInst); 906692SN/A break; 916692SN/A } 926692SN/A 936692SN/A if (fault == NoFault) { 946692SN/A MiscReg FFLAGS = xc->readMiscReg(MISCREG_FFLAGS); 956692SN/A std::feclearexcept(FE_ALL_EXCEPT); 966692SN/A %(code)s; 976692SN/A if (std::fetestexcept(FE_INEXACT)) { 986692SN/A FFLAGS |= FloatInexact; 996692SN/A } 1006692SN/A if (std::fetestexcept(FE_UNDERFLOW)) { 1019885Sstever@gmail.com FFLAGS |= FloatUnderflow; 1026692SN/A } 1036692SN/A if (std::fetestexcept(FE_OVERFLOW)) { 1046692SN/A FFLAGS |= FloatOverflow; 1056692SN/A } 1066692SN/A if (std::fetestexcept(FE_DIVBYZERO)) { 1076692SN/A FFLAGS |= FloatDivZero; 1086692SN/A } 1096692SN/A if (std::fetestexcept(FE_INVALID)) { 1106692SN/A FFLAGS |= FloatInvalid; 1116692SN/A } 1129885Sstever@gmail.com xc->setMiscReg(MISCREG_FFLAGS, FFLAGS); 1139885Sstever@gmail.com } 1149885Sstever@gmail.com 1159885Sstever@gmail.com if (fault == NoFault) { 1169885Sstever@gmail.com %(op_wb)s; 1176692SN/A } 1189055Ssaidi@eecs.umich.edu } 1199885Sstever@gmail.com return fault; 1206692SN/A } 1219885Sstever@gmail.com}}; 1227524SN/A 1239150SAli.Saidi@ARM.comdef format FPROp(code, *opt_flags) {{ 1249150SAli.Saidi@ARM.com iop = InstObjParams(name, Name, 'RegOp', code, opt_flags) 1258983Snate@binkert.org header_output = BasicDeclare.subst(iop) 1266692SN/A decoder_output = BasicConstructor.subst(iop) 1276692SN/A decode_block = BasicDecode.subst(iop) 1288983Snate@binkert.org exec_output = FloatExecute.subst(iop) 1299276Snilay@cs.wisc.edu}}; 1309885Sstever@gmail.com