basic.isa revision 12236:126ac9da6050
12929Sktlim@umich.edu// -*- mode:c++ -*- 22929Sktlim@umich.edu 32932Sktlim@umich.edu// Copyright (c) 2015 RISC-V Foundation 42929Sktlim@umich.edu// Copyright (c) 2016 The University of Virginia 52929Sktlim@umich.edu// All rights reserved. 62929Sktlim@umich.edu// 72929Sktlim@umich.edu// Redistribution and use in source and binary forms, with or without 82929Sktlim@umich.edu// modification, are permitted provided that the following conditions are 92929Sktlim@umich.edu// met: redistributions of source code must retain the above copyright 102929Sktlim@umich.edu// notice, this list of conditions and the following disclaimer; 112929Sktlim@umich.edu// redistributions in binary form must reproduce the above copyright 122929Sktlim@umich.edu// notice, this list of conditions and the following disclaimer in the 132929Sktlim@umich.edu// documentation and/or other materials provided with the distribution; 142929Sktlim@umich.edu// neither the name of the copyright holders nor the names of its 152929Sktlim@umich.edu// contributors may be used to endorse or promote products derived from 162929Sktlim@umich.edu// this software without specific prior written permission. 172929Sktlim@umich.edu// 182929Sktlim@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 192929Sktlim@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 202929Sktlim@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 212929Sktlim@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 222929Sktlim@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 232929Sktlim@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 242929Sktlim@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 252929Sktlim@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 262929Sktlim@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 272929Sktlim@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 282932Sktlim@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 292932Sktlim@umich.edu// 302932Sktlim@umich.edu// Authors: Maxwell Walter 312929Sktlim@umich.edu// Alec Roelke 326007Ssteve.reinhardt@amd.com 337735SAli.Saidi@ARM.com// Basic instruction class declaration template. 342929Sktlim@umich.edudef template BasicDeclare {{ 352929Sktlim@umich.edu // 362929Sktlim@umich.edu // Static instruction class for "%(mnemonic)s". 372929Sktlim@umich.edu // 382929Sktlim@umich.edu class %(class_name)s : public %(base_class)s 392929Sktlim@umich.edu { 402929Sktlim@umich.edu public: 412929Sktlim@umich.edu /// Constructor. 422929Sktlim@umich.edu %(class_name)s(MachInst machInst); 432929Sktlim@umich.edu Fault execute(ExecContext *, Trace::InstRecord *) const; 442929Sktlim@umich.edu using %(base_class)s::generateDisassembly; 452929Sktlim@umich.edu }; 462929Sktlim@umich.edu}}; 476007Ssteve.reinhardt@amd.com 486007Ssteve.reinhardt@amd.com// Basic instruction class constructor template. 496007Ssteve.reinhardt@amd.comdef template BasicConstructor {{ 506007Ssteve.reinhardt@amd.com %(class_name)s::%(class_name)s(MachInst machInst) 516007Ssteve.reinhardt@amd.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 526007Ssteve.reinhardt@amd.com { 536007Ssteve.reinhardt@amd.com %(constructor)s; 546007Ssteve.reinhardt@amd.com } 556007Ssteve.reinhardt@amd.com}}; 566007Ssteve.reinhardt@amd.com 576007Ssteve.reinhardt@amd.com 586007Ssteve.reinhardt@amd.com// Basic instruction class execute method template. 596007Ssteve.reinhardt@amd.comdef template BasicExecute {{ 606007Ssteve.reinhardt@amd.com Fault 616007Ssteve.reinhardt@amd.com %(class_name)s::execute(ExecContext *xc, 626007Ssteve.reinhardt@amd.com Trace::InstRecord *traceData) const 636007Ssteve.reinhardt@amd.com { 646007Ssteve.reinhardt@amd.com Fault fault = NoFault; 656007Ssteve.reinhardt@amd.com 666007Ssteve.reinhardt@amd.com %(op_decl)s; 676007Ssteve.reinhardt@amd.com %(op_rd)s; 686007Ssteve.reinhardt@amd.com if (fault == NoFault) { 696007Ssteve.reinhardt@amd.com %(code)s; 706007Ssteve.reinhardt@amd.com if (fault == NoFault) { 716007Ssteve.reinhardt@amd.com %(op_wb)s; 726007Ssteve.reinhardt@amd.com } 736007Ssteve.reinhardt@amd.com } 746007Ssteve.reinhardt@amd.com return fault; 756007Ssteve.reinhardt@amd.com } 762929Sktlim@umich.edu}}; 772929Sktlim@umich.edu 782929Sktlim@umich.edu// Basic decode template. 796007Ssteve.reinhardt@amd.comdef template BasicDecode {{ 806007Ssteve.reinhardt@amd.com return new %(class_name)s(machInst); 816007Ssteve.reinhardt@amd.com}}; 826007Ssteve.reinhardt@amd.com 836007Ssteve.reinhardt@amd.com// The most basic instruction format... 846007Ssteve.reinhardt@amd.comdef format BasicOp(code, *flags) {{ 852929Sktlim@umich.edu iop = InstObjParams(name, Name, 'RiscvStaticInst', code, flags) 862929Sktlim@umich.edu header_output = BasicDeclare.subst(iop) 872929Sktlim@umich.edu decoder_output = BasicConstructor.subst(iop) 882929Sktlim@umich.edu decode_block = BasicDecode.subst(iop) 892929Sktlim@umich.edu exec_output = BasicExecute.subst(iop) 906011Ssteve.reinhardt@amd.com}}; 916007Ssteve.reinhardt@amd.com