isa.hh revision 12106:7784fac1b159
1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * Copyright (c) 2014 Sven Karlsson 5 * Copyright (c) 2016 RISC-V Foundation 6 * Copyright (c) 2016 The University of Virginia 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are 11 * met: redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer; 13 * redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution; 16 * neither the name of the copyright holders nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Authors: Gabe Black 33 * Timothy M. Jones 34 * Sven Karlsson 35 * Alec Roelke 36 */ 37 38#ifndef __ARCH_RISCV_ISA_HH__ 39#define __ARCH_RISCV_ISA_HH__ 40 41#include <map> 42#include <string> 43 44#include "arch/riscv/registers.hh" 45#include "arch/riscv/types.hh" 46#include "base/misc.hh" 47#include "cpu/reg_class.hh" 48#include "sim/sim_object.hh" 49 50struct RiscvISAParams; 51class ThreadContext; 52class Checkpoint; 53class EventManager; 54 55namespace RiscvISA 56{ 57 58class ISA : public SimObject 59{ 60 protected: 61 std::vector<MiscReg> miscRegFile; 62 std::map<int, std::string> miscRegNames; 63 64 public: 65 typedef RiscvISAParams Params; 66 67 void 68 clear(); 69 70 MiscReg 71 readMiscRegNoEffect(int misc_reg) const; 72 73 MiscReg 74 readMiscReg(int misc_reg, ThreadContext *tc); 75 76 void 77 setMiscRegNoEffect(int misc_reg, const MiscReg &val); 78 79 void 80 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc); 81 82 RegId 83 flattenRegId(const RegId ®Id) const 84 { 85 return regId; 86 } 87 88 int 89 flattenIntIndex(int reg) const 90 { 91 return reg; 92 } 93 94 int 95 flattenFloatIndex(int reg) const 96 { 97 return reg; 98 } 99 100 // dummy 101 int 102 flattenCCIndex(int reg) const 103 { 104 return reg; 105 } 106 107 int 108 flattenMiscIndex(int reg) const 109 { 110 return reg; 111 } 112 113 void startup(ThreadContext *tc) {} 114 115 /// Explicitly import the otherwise hidden startup 116 using SimObject::startup; 117 118 const Params * 119 params() const; 120 121 ISA(Params *p); 122}; 123 124} // namespace RiscvISA 125 126#endif // __ARCH_RISCV_ISA_HH__ 127