isa.cc revision 12119:e9ef3ee3171d 
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31#include "arch/riscv/isa.hh"
32
33#include <ctime>
34#include <set>
35#include <sstream>
36
37#include "arch/riscv/registers.hh"
38#include "base/bitfield.hh"
39#include "cpu/base.hh"
40#include "debug/RiscvMisc.hh"
41#include "params/RiscvISA.hh"
42#include "sim/core.hh"
43#include "sim/pseudo_inst.hh"
44
45namespace RiscvISA
46{
47
48ISA::ISA(Params *p) : SimObject(p)
49{
50    miscRegFile.resize(NumMiscRegs);
51    clear();
52}
53
54const RiscvISAParams *
55ISA::params() const
56{
57    return dynamic_cast<const Params *>(_params);
58}
59
60void ISA::clear()
61{
62    std::fill(miscRegFile.begin(), miscRegFile.end(), 0);
63
64    miscRegFile[MISCREG_MVENDORID] = 0;
65    miscRegFile[MISCREG_MARCHID] = 0;
66    miscRegFile[MISCREG_MIMPID] = 0;
67    miscRegFile[MISCREG_MISA] = 0x8000000000101129ULL;
68}
69
70
71MiscReg
72ISA::readMiscRegNoEffect(int misc_reg) const
73{
74    DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
75        MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
76    switch (misc_reg) {
77      case MISCREG_FFLAGS:
78        return bits(miscRegFile[MISCREG_FCSR], 4, 0);
79      case MISCREG_FRM:
80        return bits(miscRegFile[MISCREG_FCSR], 7, 5);
81      case MISCREG_FCSR:
82        return bits(miscRegFile[MISCREG_FCSR], 31, 0);
83      case MISCREG_CYCLE:
84        warn("Use readMiscReg to read the cycle CSR.");
85        return 0;
86      case MISCREG_TIME:
87        return std::time(nullptr);
88      case MISCREG_INSTRET:
89        warn("Use readMiscReg to read the instret CSR.");
90        return 0;
91      case MISCREG_CYCLEH:
92        warn("Use readMiscReg to read the cycleh CSR.");
93        return 0;
94      case MISCREG_TIMEH:
95        return std::time(nullptr) >> 32;
96      case MISCREG_INSTRETH:
97        warn("Use readMiscReg to read the instreth CSR.");
98        return 0;
99      case MISCREG_MHARTID:
100        warn("Use readMiscReg to read the mhartid CSR.");
101        return 0;
102      default:
103        return miscRegFile[misc_reg];
104    }
105}
106
107MiscReg
108ISA::readMiscReg(int misc_reg, ThreadContext *tc)
109{
110    switch (misc_reg) {
111      case MISCREG_INSTRET:
112        DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
113            MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
114        return tc->getCpuPtr()->totalInsts();
115      case MISCREG_CYCLE:
116        DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
117            MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
118        return tc->getCpuPtr()->curCycle();
119      case MISCREG_INSTRETH:
120        DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
121            MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
122        return tc->getCpuPtr()->totalInsts() >> 32;
123      case MISCREG_CYCLEH:
124        DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
125            MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
126        return tc->getCpuPtr()->curCycle() >> 32;
127      case MISCREG_MHARTID:
128        return 0; // TODO: make this the hardware thread or cpu id
129      default:
130        return readMiscRegNoEffect(misc_reg);
131    }
132}
133
134void
135ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
136{
137    DPRINTF(RiscvMisc, "Setting CSR %s to 0x%016llx.\n",
138        MiscRegNames.at(misc_reg), val);
139    switch (misc_reg) {
140      case MISCREG_FFLAGS:
141        miscRegFile[MISCREG_FCSR] &= ~0x1F;
142        miscRegFile[MISCREG_FCSR] |= bits(val, 4, 0);
143        break;
144      case MISCREG_FRM:
145        miscRegFile[MISCREG_FCSR] &= ~0x70;
146        miscRegFile[MISCREG_FCSR] |= bits(val, 2, 0) << 5;
147        break;
148      case MISCREG_FCSR:
149        miscRegFile[MISCREG_FCSR] = bits(val, 7, 0);
150        break;
151      default:
152        miscRegFile[misc_reg] = val;
153        break;
154    }
155}
156
157void
158ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
159{
160    if (bits((unsigned)misc_reg, 11, 10) == 0x3) {
161        warn("Ignoring write to read-only CSR.");
162        return;
163    }
164    setMiscRegNoEffect(misc_reg, val);
165}
166
167}
168
169RiscvISA::ISA *
170RiscvISAParams::create()
171{
172    return new RiscvISA::ISA(this);
173}
174