interrupts.hh revision 12808 
1/*
2 * Copyright (c) 2011 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_RISCV_INTERRUPT_HH__
32#define __ARCH_RISCV_INTERRUPT_HH__
33
34#include "base/logging.hh"
35#include "cpu/thread_context.hh"
36#include "params/RiscvInterrupts.hh"
37#include "sim/sim_object.hh"
38
39class BaseCPU;
40class ThreadContext;
41
42namespace RiscvISA {
43
44class Interrupts : public SimObject
45{
46  private:
47    BaseCPU * cpu;
48
49  public:
50    typedef RiscvInterruptsParams Params;
51
52    const Params *
53    params() const
54    {
55        return dynamic_cast<const Params *>(_params);
56    }
57
58    Interrupts(Params * p) : SimObject(p), cpu(nullptr)
59    {}
60
61    void
62    setCPU(BaseCPU * _cpu)
63    {
64        cpu = _cpu;
65    }
66
67    void
68    post(int int_num, int index)
69    {
70        panic("Interrupts::post not implemented.\n");
71    }
72
73    void
74    clear(int int_num, int index)
75    {
76        panic("Interrupts::clear not implemented.\n");
77    }
78
79    void
80    clearAll()
81    {
82        warn_once("Interrupts::clearAll not implemented.\n");
83    }
84
85    bool
86    checkInterrupts(ThreadContext *tc) const
87    {
88        warn_once("Interrupts::checkInterrupts just rudimentary implemented");
89        /**
90         * read the machine interrupt register in order to check if interrupts
91         * are pending
92         * should be sufficient for now, as interrupts
93         * are not implemented at all
94         */
95        if (tc->readMiscReg(MISCREG_IP))
96            return true;
97
98        return false;
99    }
100
101    Fault
102    getInterrupt(ThreadContext *tc)
103    {
104        assert(checkInterrupts(tc));
105        panic("Interrupts::getInterrupt not implemented.\n");
106    }
107
108    void
109    updateIntrInfo(ThreadContext *tc)
110    {
111        panic("Interrupts::updateIntrInfo not implemented.\n");
112    }
113};
114
115} // namespace RiscvISA
116
117#endif // __ARCH_RISCV_INTERRUPT_HH__
118
119