static_inst.hh revision 12309:326eb6251659 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are
9// met: redistributions of source code must retain the above copyright
10// notice, this list of conditions and the following disclaimer;
11// redistributions in binary form must reproduce the above copyright
12// notice, this list of conditions and the following disclaimer in the
13// documentation and/or other materials provided with the distribution;
14// neither the name of the copyright holders nor the names of its
15// contributors may be used to endorse or promote products derived from
16// this software without specific prior written permission.
17//
18// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Maxwell Walter
31//          Alec Roelke
32
33#ifndef __ARCH_RISCV_STATIC_INST_HH__
34#define __ARCH_RISCV_STATIC_INST_HH__
35
36#include <string>
37
38#include "arch/riscv/types.hh"
39#include "cpu/exec_context.hh"
40#include "cpu/static_inst.hh"
41#include "mem/packet.hh"
42
43namespace RiscvISA
44{
45
46/**
47 * Base class for all RISC-V static instructions.
48 */
49class RiscvStaticInst : public StaticInst
50{
51  protected:
52    using StaticInst::StaticInst;
53
54    virtual std::string
55    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
56
57  public:
58    void advancePC(PCState &pc) const { pc.advance(); }
59};
60
61/**
62 * Base class for all RISC-V Macroops
63 */
64class RiscvMacroInst : public RiscvStaticInst
65{
66  protected:
67    std::vector<StaticInstPtr> microops;
68
69    // Constructor
70    RiscvMacroInst(const char *mnem, ExtMachInst _machInst,
71                   OpClass __opClass) :
72            RiscvStaticInst(mnem, _machInst, __opClass)
73    {
74        flags[IsMacroop] = true;
75    }
76
77    ~RiscvMacroInst() { microops.clear(); }
78
79    StaticInstPtr fetchMicroop(MicroPC upc) const { return microops[upc]; }
80
81    Fault
82    initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
83    {
84        panic("Tried to execute a macroop directly!\n");
85    }
86
87    Fault
88    completeAcc(PacketPtr pkt, ExecContext *xc,
89                Trace::InstRecord *traceData) const
90    {
91        panic("Tried to execute a macroop directly!\n");
92    }
93
94    Fault
95    execute(ExecContext *xc, Trace::InstRecord *traceData) const
96    {
97        panic("Tried to execute a macroop directly!\n");
98    }
99};
100
101/**
102 * Base class for all RISC-V Microops
103 */
104class RiscvMicroInst : public RiscvStaticInst
105{
106  protected:
107    // Constructor
108    RiscvMicroInst(const char *mnem, ExtMachInst _machInst,
109                   OpClass __opClass) :
110            RiscvStaticInst(mnem, _machInst, __opClass)
111    {
112        flags[IsMicroop] = true;
113    }
114
115    void advancePC(PCState &pcState) const;
116};
117
118}
119
120#endif // __ARCH_RISCV_STATIC_INST_HH__
121