static_inst.hh revision 12482
112326Sar4jc@virginia.edu/* 212326Sar4jc@virginia.edu * Copyright (c) 2015 RISC-V Foundation 312326Sar4jc@virginia.edu * Copyright (c) 2016 The University of Virginia 412326Sar4jc@virginia.edu * All rights reserved. 512326Sar4jc@virginia.edu * 612326Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 712326Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 812326Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 912326Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 1012326Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1112326Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1212326Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1312326Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1412326Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1512326Sar4jc@virginia.edu * this software without specific prior written permission. 1612326Sar4jc@virginia.edu * 1712326Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812326Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912326Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012326Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112326Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212326Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312326Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412326Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512326Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612326Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2712326Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2812326Sar4jc@virginia.edu * 2912326Sar4jc@virginia.edu * Authors: Maxwell Walter 3012326Sar4jc@virginia.edu * Alec Roelke 3112326Sar4jc@virginia.edu */ 3212309Sar4jc@virginia.edu 3312309Sar4jc@virginia.edu#ifndef __ARCH_RISCV_STATIC_INST_HH__ 3412309Sar4jc@virginia.edu#define __ARCH_RISCV_STATIC_INST_HH__ 3512309Sar4jc@virginia.edu 3612309Sar4jc@virginia.edu#include <string> 3712309Sar4jc@virginia.edu 3812309Sar4jc@virginia.edu#include "arch/riscv/types.hh" 3912309Sar4jc@virginia.edu#include "cpu/exec_context.hh" 4012309Sar4jc@virginia.edu#include "cpu/static_inst.hh" 4112309Sar4jc@virginia.edu#include "mem/packet.hh" 4212309Sar4jc@virginia.edu 4312309Sar4jc@virginia.edunamespace RiscvISA 4412309Sar4jc@virginia.edu{ 4512309Sar4jc@virginia.edu 4612309Sar4jc@virginia.edu/** 4712309Sar4jc@virginia.edu * Base class for all RISC-V static instructions. 4812309Sar4jc@virginia.edu */ 4912309Sar4jc@virginia.educlass RiscvStaticInst : public StaticInst 5012309Sar4jc@virginia.edu{ 5112309Sar4jc@virginia.edu protected: 5212309Sar4jc@virginia.edu using StaticInst::StaticInst; 5312309Sar4jc@virginia.edu 5412309Sar4jc@virginia.edu virtual std::string 5512309Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 5612309Sar4jc@virginia.edu 5712309Sar4jc@virginia.edu public: 5812309Sar4jc@virginia.edu void advancePC(PCState &pc) const { pc.advance(); } 5912309Sar4jc@virginia.edu}; 6012309Sar4jc@virginia.edu 6112309Sar4jc@virginia.edu/** 6212309Sar4jc@virginia.edu * Base class for all RISC-V Macroops 6312309Sar4jc@virginia.edu */ 6412309Sar4jc@virginia.educlass RiscvMacroInst : public RiscvStaticInst 6512309Sar4jc@virginia.edu{ 6612309Sar4jc@virginia.edu protected: 6712309Sar4jc@virginia.edu std::vector<StaticInstPtr> microops; 6812309Sar4jc@virginia.edu 6912309Sar4jc@virginia.edu RiscvMacroInst(const char *mnem, ExtMachInst _machInst, 7012309Sar4jc@virginia.edu OpClass __opClass) : 7112309Sar4jc@virginia.edu RiscvStaticInst(mnem, _machInst, __opClass) 7212309Sar4jc@virginia.edu { 7312309Sar4jc@virginia.edu flags[IsMacroop] = true; 7412309Sar4jc@virginia.edu } 7512309Sar4jc@virginia.edu 7612309Sar4jc@virginia.edu ~RiscvMacroInst() { microops.clear(); } 7712309Sar4jc@virginia.edu 7812482Sgabeblack@google.com StaticInstPtr 7912482Sgabeblack@google.com fetchMicroop(MicroPC upc) const override 8012482Sgabeblack@google.com { 8112482Sgabeblack@google.com return microops[upc]; 8212482Sgabeblack@google.com } 8312309Sar4jc@virginia.edu 8412309Sar4jc@virginia.edu Fault 8512482Sgabeblack@google.com initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override 8612309Sar4jc@virginia.edu { 8712309Sar4jc@virginia.edu panic("Tried to execute a macroop directly!\n"); 8812309Sar4jc@virginia.edu } 8912309Sar4jc@virginia.edu 9012309Sar4jc@virginia.edu Fault 9112309Sar4jc@virginia.edu completeAcc(PacketPtr pkt, ExecContext *xc, 9212482Sgabeblack@google.com Trace::InstRecord *traceData) const override 9312309Sar4jc@virginia.edu { 9412309Sar4jc@virginia.edu panic("Tried to execute a macroop directly!\n"); 9512309Sar4jc@virginia.edu } 9612309Sar4jc@virginia.edu 9712309Sar4jc@virginia.edu Fault 9812482Sgabeblack@google.com execute(ExecContext *xc, Trace::InstRecord *traceData) const override 9912309Sar4jc@virginia.edu { 10012309Sar4jc@virginia.edu panic("Tried to execute a macroop directly!\n"); 10112309Sar4jc@virginia.edu } 10212309Sar4jc@virginia.edu}; 10312309Sar4jc@virginia.edu 10412309Sar4jc@virginia.edu/** 10512309Sar4jc@virginia.edu * Base class for all RISC-V Microops 10612309Sar4jc@virginia.edu */ 10712309Sar4jc@virginia.educlass RiscvMicroInst : public RiscvStaticInst 10812309Sar4jc@virginia.edu{ 10912309Sar4jc@virginia.edu protected: 11012309Sar4jc@virginia.edu RiscvMicroInst(const char *mnem, ExtMachInst _machInst, 11112309Sar4jc@virginia.edu OpClass __opClass) : 11212309Sar4jc@virginia.edu RiscvStaticInst(mnem, _machInst, __opClass) 11312309Sar4jc@virginia.edu { 11412309Sar4jc@virginia.edu flags[IsMicroop] = true; 11512309Sar4jc@virginia.edu } 11612309Sar4jc@virginia.edu 11712309Sar4jc@virginia.edu void advancePC(PCState &pcState) const; 11812309Sar4jc@virginia.edu}; 11912309Sar4jc@virginia.edu 12012309Sar4jc@virginia.edu} 12112309Sar4jc@virginia.edu 12212309Sar4jc@virginia.edu#endif // __ARCH_RISCV_STATIC_INST_HH__ 123