amo.hh revision 12323
1/* 2 * Copyright (c) 2015 RISC-V Foundation 3 * Copyright (c) 2017 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Alec Roelke 30 */ 31 32#ifndef __ARCH_RISCV_INSTS_AMO_HH__ 33#define __ARCH_RISCV_INSTS_AMO_HH__ 34 35#include <string> 36 37#include "arch/riscv/insts/mem.hh" 38#include "arch/riscv/insts/static_inst.hh" 39#include "cpu/static_inst.hh" 40 41namespace RiscvISA 42{ 43 44class LoadReserved : public MemInst 45{ 46 protected: 47 using MemInst::MemInst; 48 49 std::string generateDisassembly( 50 Addr pc, const SymbolTable *symtab) const override; 51}; 52 53class StoreCond : public MemInst 54{ 55 protected: 56 using MemInst::MemInst; 57 58 std::string generateDisassembly( 59 Addr pc, const SymbolTable *symtab) const override; 60}; 61 62class AtomicMemOp : public RiscvMacroInst 63{ 64 protected: 65 using RiscvMacroInst::RiscvMacroInst; 66 67 std::string generateDisassembly( 68 Addr pc, const SymbolTable *symtab) const override; 69}; 70 71class AtomicMemOpMicro : public RiscvMicroInst 72{ 73 protected: 74 Request::Flags memAccessFlags; 75 using RiscvMicroInst::RiscvMicroInst; 76 77 std::string generateDisassembly( 78 Addr pc, const SymbolTable *symtab) const override; 79}; 80 81} 82 83#endif // __ARCH_RISCV_INSTS_AMO_HH__