amo.hh revision 13653
112323Sar4jc@virginia.edu/* 212323Sar4jc@virginia.edu * Copyright (c) 2015 RISC-V Foundation 312323Sar4jc@virginia.edu * Copyright (c) 2017 The University of Virginia 412323Sar4jc@virginia.edu * All rights reserved. 512323Sar4jc@virginia.edu * 612323Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 712323Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 812323Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 912323Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 1012323Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1112323Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1212323Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1312323Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1412323Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1512323Sar4jc@virginia.edu * this software without specific prior written permission. 1612323Sar4jc@virginia.edu * 1712323Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812323Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912323Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012323Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112323Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212323Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312323Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412323Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512323Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612323Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2712323Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2812323Sar4jc@virginia.edu * 2912323Sar4jc@virginia.edu * Authors: Alec Roelke 3012323Sar4jc@virginia.edu */ 3112323Sar4jc@virginia.edu 3212323Sar4jc@virginia.edu#ifndef __ARCH_RISCV_INSTS_AMO_HH__ 3312323Sar4jc@virginia.edu#define __ARCH_RISCV_INSTS_AMO_HH__ 3412323Sar4jc@virginia.edu 3512323Sar4jc@virginia.edu#include <string> 3612323Sar4jc@virginia.edu 3712323Sar4jc@virginia.edu#include "arch/riscv/insts/mem.hh" 3812323Sar4jc@virginia.edu#include "arch/riscv/insts/static_inst.hh" 3912323Sar4jc@virginia.edu#include "cpu/static_inst.hh" 4012323Sar4jc@virginia.edu 4112323Sar4jc@virginia.edunamespace RiscvISA 4212323Sar4jc@virginia.edu{ 4312323Sar4jc@virginia.edu 4413653Sqtt2@cornell.edu// memfence micro instruction 4513653Sqtt2@cornell.educlass MemFenceMicro : public RiscvMicroInst 4613653Sqtt2@cornell.edu{ 4713653Sqtt2@cornell.edu public: 4813653Sqtt2@cornell.edu MemFenceMicro(ExtMachInst _machInst, OpClass __opClass) 4913653Sqtt2@cornell.edu : RiscvMicroInst("fence", _machInst, __opClass) 5013653Sqtt2@cornell.edu { } 5113653Sqtt2@cornell.edu protected: 5213653Sqtt2@cornell.edu using RiscvMicroInst::RiscvMicroInst; 5313653Sqtt2@cornell.edu 5413653Sqtt2@cornell.edu Fault execute(ExecContext *, Trace::InstRecord *) const override; 5513653Sqtt2@cornell.edu std::string generateDisassembly( 5613653Sqtt2@cornell.edu Addr pc, const SymbolTable *symtab) const override; 5713653Sqtt2@cornell.edu}; 5813653Sqtt2@cornell.edu 5913653Sqtt2@cornell.edu// load-reserved 6013653Sqtt2@cornell.educlass LoadReserved : public RiscvMacroInst 6112323Sar4jc@virginia.edu{ 6212323Sar4jc@virginia.edu protected: 6313653Sqtt2@cornell.edu using RiscvMacroInst::RiscvMacroInst; 6412323Sar4jc@virginia.edu 6512323Sar4jc@virginia.edu std::string generateDisassembly( 6612323Sar4jc@virginia.edu Addr pc, const SymbolTable *symtab) const override; 6712323Sar4jc@virginia.edu}; 6812323Sar4jc@virginia.edu 6913653Sqtt2@cornell.educlass LoadReservedMicro : public RiscvMicroInst 7012323Sar4jc@virginia.edu{ 7112323Sar4jc@virginia.edu protected: 7213653Sqtt2@cornell.edu Request::Flags memAccessFlags; 7313653Sqtt2@cornell.edu using RiscvMicroInst::RiscvMicroInst; 7412323Sar4jc@virginia.edu 7512323Sar4jc@virginia.edu std::string generateDisassembly( 7612323Sar4jc@virginia.edu Addr pc, const SymbolTable *symtab) const override; 7712323Sar4jc@virginia.edu}; 7812323Sar4jc@virginia.edu 7913653Sqtt2@cornell.edu// store-cond 8013653Sqtt2@cornell.educlass StoreCond : public RiscvMacroInst 8113653Sqtt2@cornell.edu{ 8213653Sqtt2@cornell.edu protected: 8313653Sqtt2@cornell.edu using RiscvMacroInst::RiscvMacroInst; 8413653Sqtt2@cornell.edu 8513653Sqtt2@cornell.edu std::string generateDisassembly( 8613653Sqtt2@cornell.edu Addr pc, const SymbolTable *symtab) const override; 8713653Sqtt2@cornell.edu}; 8813653Sqtt2@cornell.edu 8913653Sqtt2@cornell.educlass StoreCondMicro : public RiscvMicroInst 9013653Sqtt2@cornell.edu{ 9113653Sqtt2@cornell.edu protected: 9213653Sqtt2@cornell.edu Request::Flags memAccessFlags; 9313653Sqtt2@cornell.edu using RiscvMicroInst::RiscvMicroInst; 9413653Sqtt2@cornell.edu 9513653Sqtt2@cornell.edu std::string generateDisassembly( 9613653Sqtt2@cornell.edu Addr pc, const SymbolTable *symtab) const override; 9713653Sqtt2@cornell.edu}; 9813653Sqtt2@cornell.edu 9913653Sqtt2@cornell.edu// AMOs 10012323Sar4jc@virginia.educlass AtomicMemOp : public RiscvMacroInst 10112323Sar4jc@virginia.edu{ 10212323Sar4jc@virginia.edu protected: 10312323Sar4jc@virginia.edu using RiscvMacroInst::RiscvMacroInst; 10412323Sar4jc@virginia.edu 10512323Sar4jc@virginia.edu std::string generateDisassembly( 10612323Sar4jc@virginia.edu Addr pc, const SymbolTable *symtab) const override; 10712323Sar4jc@virginia.edu}; 10812323Sar4jc@virginia.edu 10912323Sar4jc@virginia.educlass AtomicMemOpMicro : public RiscvMicroInst 11012323Sar4jc@virginia.edu{ 11112323Sar4jc@virginia.edu protected: 11212323Sar4jc@virginia.edu Request::Flags memAccessFlags; 11312323Sar4jc@virginia.edu using RiscvMicroInst::RiscvMicroInst; 11412323Sar4jc@virginia.edu 11512323Sar4jc@virginia.edu std::string generateDisassembly( 11612323Sar4jc@virginia.edu Addr pc, const SymbolTable *symtab) const override; 11712323Sar4jc@virginia.edu}; 11812323Sar4jc@virginia.edu 11913653Sqtt2@cornell.edu/** 12013653Sqtt2@cornell.edu * A generic atomic op class 12113653Sqtt2@cornell.edu */ 12213653Sqtt2@cornell.edu 12313653Sqtt2@cornell.edutemplate<typename T> 12413653Sqtt2@cornell.educlass AtomicGenericOp : public TypedAtomicOpFunctor<T> 12513653Sqtt2@cornell.edu{ 12613653Sqtt2@cornell.edu public: 12713653Sqtt2@cornell.edu AtomicGenericOp(T _a, std::function<void(T*,T)> _op) 12813653Sqtt2@cornell.edu : a(_a), op(_op) { } 12913653Sqtt2@cornell.edu AtomicOpFunctor* clone() { return new AtomicGenericOp<T>(*this); } 13013653Sqtt2@cornell.edu void execute(T *b) { op(b, a); } 13113653Sqtt2@cornell.edu private: 13213653Sqtt2@cornell.edu T a; 13313653Sqtt2@cornell.edu std::function<void(T*,T)> op; 13413653Sqtt2@cornell.edu}; 13513653Sqtt2@cornell.edu 13612323Sar4jc@virginia.edu} 13712323Sar4jc@virginia.edu 13813653Sqtt2@cornell.edu#endif // __ARCH_RISCV_INSTS_AMO_HH__ 139