faults.hh revision 12850:7036cad54910 
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Alec Roelke
31 *          Robert Scheffel
32 */
33
34#ifndef __ARCH_RISCV_FAULTS_HH__
35#define __ARCH_RISCV_FAULTS_HH__
36
37#include <map>
38#include <string>
39
40#include "arch/riscv/isa.hh"
41#include "arch/riscv/registers.hh"
42#include "cpu/thread_context.hh"
43#include "sim/faults.hh"
44
45namespace RiscvISA
46{
47
48enum FloatException : MiscReg {
49    FloatInexact = 0x1,
50    FloatUnderflow = 0x2,
51    FloatOverflow = 0x4,
52    FloatDivZero = 0x8,
53    FloatInvalid = 0x10
54};
55
56enum ExceptionCode : MiscReg {
57    INST_ADDR_MISALIGNED = 0,
58    INST_ACCESS = 1,
59    INST_ILLEGAL = 2,
60    BREAKPOINT = 3,
61    LOAD_ADDR_MISALIGNED = 4,
62    LOAD_ACCESS = 5,
63    STORE_ADDR_MISALIGNED = 6,
64    AMO_ADDR_MISALIGNED = 6,
65    STORE_ACCESS = 7,
66    AMO_ACCESS = 7,
67    ECALL_USER = 8,
68    ECALL_SUPER = 9,
69    ECALL_MACHINE = 11,
70    INST_PAGE = 12,
71    LOAD_PAGE = 13,
72    STORE_PAGE = 15,
73    AMO_PAGE = 15
74};
75
76class RiscvFault : public FaultBase
77{
78  protected:
79    const FaultName _name;
80    const bool _interrupt;
81    ExceptionCode _code;
82
83    RiscvFault(FaultName n, bool i, ExceptionCode c)
84        : _name(n), _interrupt(i), _code(c)
85    {}
86
87    FaultName name() const override { return _name; }
88    bool isInterrupt() const { return _interrupt; }
89    ExceptionCode exception() const { return _code; }
90    virtual MiscReg trap_value() const { return 0; }
91
92    virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
93    void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
94};
95
96class Reset : public FaultBase
97{
98
99    public:
100        Reset()
101            : _name("reset")
102        {}
103
104        FaultName
105        name() const override
106        {
107            return _name;
108        }
109
110        void
111        invoke(ThreadContext *tc, const StaticInstPtr &inst =
112            StaticInst::nullStaticInstPtr) override;
113
114    private:
115        const FaultName _name;
116};
117
118class InstFault : public RiscvFault
119{
120  protected:
121    const ExtMachInst _inst;
122
123  public:
124    InstFault(FaultName n, const ExtMachInst inst)
125        : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)
126    {}
127
128    MiscReg trap_value() const override { return _inst; }
129};
130
131class UnknownInstFault : public InstFault
132{
133  public:
134    UnknownInstFault(const ExtMachInst inst)
135        : InstFault("Unknown instruction", inst)
136    {}
137
138    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
139};
140
141class IllegalInstFault : public InstFault
142{
143  private:
144    const std::string reason;
145
146  public:
147    IllegalInstFault(std::string r, const ExtMachInst inst)
148        : InstFault("Illegal instruction", inst)
149    {}
150
151    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
152};
153
154class UnimplementedFault : public InstFault
155{
156  private:
157    const std::string instName;
158
159  public:
160    UnimplementedFault(std::string name, const ExtMachInst inst)
161        : InstFault("Unimplemented instruction", inst),
162          instName(name)
163    {}
164
165    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
166};
167
168class IllegalFrmFault: public InstFault
169{
170  private:
171    const uint8_t frm;
172
173  public:
174    IllegalFrmFault(uint8_t r, const ExtMachInst inst)
175        : InstFault("Illegal floating-point rounding mode", inst),
176          frm(r)
177    {}
178
179    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
180};
181
182class AddressFault : public RiscvFault
183{
184  private:
185    const Addr _addr;
186
187  public:
188    AddressFault(const Addr addr, ExceptionCode code)
189        : RiscvFault("Address", false, code), _addr(addr)
190    {}
191
192    MiscReg trap_value() const override { return _addr; }
193};
194
195class BreakpointFault : public RiscvFault
196{
197  private:
198    const PCState pcState;
199
200  public:
201    BreakpointFault(const PCState &pc)
202        : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc)
203    {}
204
205    MiscReg trap_value() const override { return pcState.pc(); }
206    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
207};
208
209class SyscallFault : public RiscvFault
210{
211  public:
212    SyscallFault(PrivilegeMode prv)
213        : RiscvFault("System call", false, ECALL_USER)
214    {
215        switch (prv) {
216          case PRV_U:
217            _code = ECALL_USER;
218            break;
219          case PRV_S:
220            _code = ECALL_SUPER;
221            break;
222          case PRV_M:
223            _code = ECALL_MACHINE;
224            break;
225          default:
226            panic("Unknown privilege mode %d.", prv);
227            break;
228        }
229    }
230
231    void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
232};
233
234} // namespace RiscvISA
235
236#endif // __ARCH_RISCV_FAULTS_HH__
237