faults.hh revision 12136:1070125670e2 
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31
32#ifndef __ARCH_RISCV_FAULTS_HH__
33#define __ARCH_RISCV_FAULTS_HH__
34
35#include <string>
36
37#include "cpu/thread_context.hh"
38#include "sim/faults.hh"
39
40namespace RiscvISA
41{
42
43const uint32_t FloatInexact = 1 << 0;
44const uint32_t FloatUnderflow = 1 << 1;
45const uint32_t FloatOverflow = 1 << 2;
46const uint32_t FloatDivZero = 1 << 3;
47const uint32_t FloatInvalid = 1 << 4;
48
49enum ExceptionCode {
50    INST_ADDR_MISALIGNED = 0,
51    INST_ACCESS = 1,
52    INST_ILLEGAL = 2,
53    BREAKPOINT = 3,
54    LOAD_ADDR_MISALIGNED = 4,
55    LOAD_ACCESS = 5,
56    STORE_ADDR_MISALIGNED = 6,
57    AMO_ADDR_MISALIGNED = 6,
58    STORE_ACCESS = 7,
59    AMO_ACCESS = 7,
60    ECALL_USER = 8,
61    ECALL_SUPER = 9,
62    ECALL_HYPER = 10,
63    ECALL_MACH = 11
64};
65
66enum InterruptCode {
67    SOFTWARE,
68    TIMER
69};
70
71class RiscvFault : public FaultBase
72{
73  protected:
74    const FaultName _name;
75    const ExceptionCode _code;
76    const InterruptCode _int;
77
78    RiscvFault(FaultName n, ExceptionCode c, InterruptCode i)
79        : _name(n), _code(c), _int(i)
80    {}
81
82    FaultName
83    name() const
84    {
85        return _name;
86    }
87
88    ExceptionCode
89    exception() const
90    {
91        return _code;
92    }
93
94    InterruptCode
95    interrupt() const
96    {
97        return _int;
98    }
99
100    virtual void
101    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
102
103    void
104    invoke(ThreadContext *tc, const StaticInstPtr &inst);
105};
106
107
108class UnknownInstFault : public RiscvFault
109{
110  public:
111    UnknownInstFault() : RiscvFault("Unknown instruction", INST_ILLEGAL,
112            SOFTWARE)
113    {}
114
115    void
116    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
117};
118
119class IllegalInstFault : public RiscvFault
120{
121  private:
122    const std::string reason;
123  public:
124    IllegalInstFault(std::string r)
125        : RiscvFault("Illegal instruction", INST_ILLEGAL, SOFTWARE),
126          reason(r)
127    {}
128
129    void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
130};
131
132class UnimplementedFault : public RiscvFault
133{
134  private:
135    const std::string instName;
136  public:
137    UnimplementedFault(std::string name)
138        : RiscvFault("Unimplemented instruction", INST_ILLEGAL, SOFTWARE),
139        instName(name)
140    {}
141
142    void
143    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
144};
145
146class IllegalFrmFault: public RiscvFault
147{
148  private:
149    const uint8_t frm;
150  public:
151    IllegalFrmFault(uint8_t r)
152        : RiscvFault("Illegal floating-point rounding mode", INST_ILLEGAL,
153                SOFTWARE),
154        frm(r)
155    {}
156
157    void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
158};
159
160class BreakpointFault : public RiscvFault
161{
162  public:
163    BreakpointFault() : RiscvFault("Breakpoint", BREAKPOINT, SOFTWARE)
164    {}
165
166    void
167    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
168};
169
170class SyscallFault : public RiscvFault
171{
172  public:
173    // TODO: replace ECALL_USER with the appropriate privilege level of the
174    // caller
175    SyscallFault() : RiscvFault("System call", ECALL_USER, SOFTWARE)
176    {}
177
178    void
179    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
180};
181
182} // namespace RiscvISA
183
184#endif // __ARCH_RISCV_FAULTS_HH__
185