faults.hh revision 11723 
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31
32#ifndef __ARCH_RISCV_FAULTS_HH__
33#define __ARCH_RISCV_FAULTS_HH__
34
35#include <string>
36
37#include "cpu/thread_context.hh"
38#include "sim/faults.hh"
39
40namespace RiscvISA
41{
42
43enum ExceptionCode {
44    INST_ADDR_MISALIGNED = 0,
45    INST_ACCESS = 1,
46    INST_ILLEGAL = 2,
47    BREAKPOINT = 3,
48    LOAD_ADDR_MISALIGNED = 4,
49    LOAD_ACCESS = 5,
50    STORE_ADDR_MISALIGNED = 6,
51    AMO_ADDR_MISALIGNED = 6,
52    STORE_ACCESS = 7,
53    AMO_ACCESS = 7,
54    ECALL_USER = 8,
55    ECALL_SUPER = 9,
56    ECALL_HYPER = 10,
57    ECALL_MACH = 11
58};
59
60enum InterruptCode {
61    SOFTWARE,
62    TIMER
63};
64
65class RiscvFault : public FaultBase
66{
67  protected:
68    const FaultName _name;
69    const ExceptionCode _code;
70    const InterruptCode _int;
71
72    RiscvFault(FaultName n, ExceptionCode c, InterruptCode i)
73        : _name(n), _code(c), _int(i)
74    {}
75
76    FaultName
77    name() const
78    {
79        return _name;
80    }
81
82    ExceptionCode
83    exception() const
84    {
85        return _code;
86    }
87
88    InterruptCode
89    interrupt() const
90    {
91        return _int;
92    }
93
94    virtual void
95    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
96
97    void
98    invoke(ThreadContext *tc, const StaticInstPtr &inst);
99};
100
101
102class UnknownInstFault : public RiscvFault
103{
104  public:
105    UnknownInstFault() : RiscvFault("Unknown instruction", INST_ILLEGAL,
106            SOFTWARE)
107    {}
108
109    void
110    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
111};
112
113class UnimplementedFault : public RiscvFault
114{
115  private:
116    const std::string instName;
117  public:
118    UnimplementedFault(std::string name)
119        : RiscvFault("Unimplemented instruction", INST_ILLEGAL, SOFTWARE),
120        instName(name)
121    {}
122
123    void
124    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
125};
126
127class BreakpointFault : public RiscvFault
128{
129  public:
130    BreakpointFault() : RiscvFault("Breakpoint", BREAKPOINT, SOFTWARE)
131    {}
132
133    void
134    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
135};
136
137class SyscallFault : public RiscvFault
138{
139  public:
140    // TODO: replace ECALL_USER with the appropriate privilege level of the
141    // caller
142    SyscallFault() : RiscvFault("System call", ECALL_USER, SOFTWARE)
143    {}
144
145    void
146    invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
147};
148
149} // namespace RiscvISA
150
151#endif // __ARCH_RISCV_FAULTS_HH__
152