faults.hh revision 12849
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2016 RISC-V Foundation 35643Sgblack@eecs.umich.edu * Copyright (c) 2016 The University of Virginia 45643Sgblack@eecs.umich.edu * Copyright (c) 2018 TU Dresden 55643Sgblack@eecs.umich.edu * All rights reserved. 65643Sgblack@eecs.umich.edu * 75643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 85643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 95643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 115643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 125643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 135643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 145643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 155643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 165643Sgblack@eecs.umich.edu * this software without specific prior written permission. 175643Sgblack@eecs.umich.edu * 185643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 195643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 205643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 215643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 225643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 235643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 245643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 255643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 265643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 275643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 285643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 295643Sgblack@eecs.umich.edu * 305643Sgblack@eecs.umich.edu * Authors: Alec Roelke 3111793Sbrandon.potter@amd.com * Robert Scheffel 3211793Sbrandon.potter@amd.com */ 336138Sgblack@eecs.umich.edu 345651Sgblack@eecs.umich.edu#ifndef __ARCH_RISCV_FAULTS_HH__ 358746Sgblack@eecs.umich.edu#define __ARCH_RISCV_FAULTS_HH__ 368232Snate@binkert.org 375657Sgblack@eecs.umich.edu#include <string> 385643Sgblack@eecs.umich.edu 395643Sgblack@eecs.umich.edu#include "arch/riscv/registers.hh" 405643Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 415643Sgblack@eecs.umich.edu#include "sim/faults.hh" 429805Sstever@gmail.com 439808Sstever@gmail.comnamespace RiscvISA 449805Sstever@gmail.com{ 455643Sgblack@eecs.umich.edu 467913SBrad.Beckmann@amd.comenum FloatException : MiscReg { 477913SBrad.Beckmann@amd.com FloatInexact = 0x1, 487913SBrad.Beckmann@amd.com FloatUnderflow = 0x2, 497913SBrad.Beckmann@amd.com FloatOverflow = 0x4, 507913SBrad.Beckmann@amd.com FloatDivZero = 0x8, 516136Sgblack@eecs.umich.edu FloatInvalid = 0x10 525643Sgblack@eecs.umich.edu}; 535643Sgblack@eecs.umich.edu 545653Sgblack@eecs.umich.eduenum ExceptionCode : MiscReg { 555653Sgblack@eecs.umich.edu INST_ADDR_MISALIGNED = 0, 565653Sgblack@eecs.umich.edu INST_ACCESS = 1, 575653Sgblack@eecs.umich.edu INST_ILLEGAL = 2, 585827Sgblack@eecs.umich.edu BREAKPOINT = 3, 595653Sgblack@eecs.umich.edu LOAD_ADDR_MISALIGNED = 4, 605643Sgblack@eecs.umich.edu LOAD_ACCESS = 5, 615643Sgblack@eecs.umich.edu STORE_ADDR_MISALIGNED = 6, 627913SBrad.Beckmann@amd.com AMO_ADDR_MISALIGNED = 6, 637913SBrad.Beckmann@amd.com STORE_ACCESS = 7, 647913SBrad.Beckmann@amd.com AMO_ACCESS = 7, 657913SBrad.Beckmann@amd.com ECALL_USER = 8, 667913SBrad.Beckmann@amd.com ECALL_SUPER = 9, 679807Sstever@gmail.com ECALL_MACHINE = 11, 687913SBrad.Beckmann@amd.com INST_PAGE = 12, 699805Sstever@gmail.com LOAD_PAGE = 13, 709807Sstever@gmail.com STORE_PAGE = 15, 717913SBrad.Beckmann@amd.com AMO_PAGE = 15 727913SBrad.Beckmann@amd.com}; 739805Sstever@gmail.com 749805Sstever@gmail.com/** 759805Sstever@gmail.com * These fields are specified in the RISC-V Instruction Set Manual, Volume II, 769805Sstever@gmail.com * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that 779805Sstever@gmail.com * uses these fields is the MSTATUS register, which is shadowed by two others 789805Sstever@gmail.com * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see 799805Sstever@gmail.com * the fields for higher privileges. 809805Sstever@gmail.com */ 819805Sstever@gmail.comBitUnion64(STATUS) 829805Sstever@gmail.com Bitfield<63> sd; 839805Sstever@gmail.com Bitfield<35, 34> sxl; 849805Sstever@gmail.com Bitfield<33, 32> uxl; 859805Sstever@gmail.com Bitfield<22> tsr; 869805Sstever@gmail.com Bitfield<21> tw; 879805Sstever@gmail.com Bitfield<20> tvm; 889805Sstever@gmail.com Bitfield<19> mxr; 899805Sstever@gmail.com Bitfield<18> sum; 909805Sstever@gmail.com Bitfield<17> mprv; 915643Sgblack@eecs.umich.edu Bitfield<16, 15> xs; 9211144Sjthestness@gmail.com Bitfield<14, 13> fs; 9311144Sjthestness@gmail.com Bitfield<12, 11> mpp; 9411144Sjthestness@gmail.com Bitfield<8> spp; 9511144Sjthestness@gmail.com Bitfield<7> mpie; 9611144Sjthestness@gmail.com Bitfield<5> spie; 9711144Sjthestness@gmail.com Bitfield<4> upie; 9811144Sjthestness@gmail.com Bitfield<3> mie; 9911144Sjthestness@gmail.com Bitfield<1> sie; 10011144Sjthestness@gmail.com Bitfield<0> uie; 1015643Sgblack@eecs.umich.eduEndBitUnion(STATUS) 1025643Sgblack@eecs.umich.edu 1035643Sgblack@eecs.umich.edu/** 1045643Sgblack@eecs.umich.edu * These fields are specified in the RISC-V Instruction Set Manual, Volume II, 1055643Sgblack@eecs.umich.edu * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP 1065643Sgblack@eecs.umich.edu * and MIE registers have the same fields, so accesses to either should use 1075643Sgblack@eecs.umich.edu * this bit union. 1085643Sgblack@eecs.umich.edu */ 1095643Sgblack@eecs.umich.eduBitUnion64(INTERRUPT) 1105643Sgblack@eecs.umich.edu Bitfield<11> mei; 1115643Sgblack@eecs.umich.edu Bitfield<9> sei; 1125643Sgblack@eecs.umich.edu Bitfield<8> uei; 1135643Sgblack@eecs.umich.edu Bitfield<7> mti; 1145643Sgblack@eecs.umich.edu Bitfield<5> sti; 1155898Sgblack@eecs.umich.edu Bitfield<4> uti; 1169805Sstever@gmail.com Bitfield<3> msi; 1175643Sgblack@eecs.umich.edu Bitfield<1> ssi; 1185643Sgblack@eecs.umich.edu Bitfield<0> usi; 1195643Sgblack@eecs.umich.eduEndBitUnion(INTERRUPT) 1205643Sgblack@eecs.umich.edu 1215643Sgblack@eecs.umich.educlass RiscvFault : public FaultBase 1225643Sgblack@eecs.umich.edu{ 1235643Sgblack@eecs.umich.edu protected: 1245643Sgblack@eecs.umich.edu const FaultName _name; 1255643Sgblack@eecs.umich.edu bool _interrupt; 1265643Sgblack@eecs.umich.edu const ExceptionCode _code; 1275643Sgblack@eecs.umich.edu 1285643Sgblack@eecs.umich.edu RiscvFault(FaultName n, bool i, ExceptionCode c) 1295643Sgblack@eecs.umich.edu : _name(n), _interrupt(i), _code(c) 1305643Sgblack@eecs.umich.edu {} 1315643Sgblack@eecs.umich.edu 1325643Sgblack@eecs.umich.edu FaultName name() const override { return _name; } 1335643Sgblack@eecs.umich.edu bool isInterrupt() const { return _interrupt; } 1345898Sgblack@eecs.umich.edu ExceptionCode exception() const { return _code; } 1359805Sstever@gmail.com virtual MiscReg trap_value() const { return 0; } 1365643Sgblack@eecs.umich.edu 1375643Sgblack@eecs.umich.edu virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst); 1385643Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 1395643Sgblack@eecs.umich.edu}; 1405643Sgblack@eecs.umich.edu 1415643Sgblack@eecs.umich.educlass Reset : public FaultBase 1427913SBrad.Beckmann@amd.com{ 1435643Sgblack@eecs.umich.edu 1445643Sgblack@eecs.umich.edu public: 1455643Sgblack@eecs.umich.edu Reset() 1467913SBrad.Beckmann@amd.com : _name("reset") 1475643Sgblack@eecs.umich.edu {} 1485643Sgblack@eecs.umich.edu 1495643Sgblack@eecs.umich.edu FaultName 1505643Sgblack@eecs.umich.edu name() const override 1515643Sgblack@eecs.umich.edu { 1525643Sgblack@eecs.umich.edu return _name; 1535643Sgblack@eecs.umich.edu } 1545643Sgblack@eecs.umich.edu 1555643Sgblack@eecs.umich.edu void 1565643Sgblack@eecs.umich.edu invoke(ThreadContext *tc, const StaticInstPtr &inst = 1575643Sgblack@eecs.umich.edu StaticInst::nullStaticInstPtr) override; 1585643Sgblack@eecs.umich.edu 1595643Sgblack@eecs.umich.edu private: 1605643Sgblack@eecs.umich.edu const FaultName _name; 1615643Sgblack@eecs.umich.edu}; 1625643Sgblack@eecs.umich.edu 1635643Sgblack@eecs.umich.educlass InstFault : public RiscvFault 1645643Sgblack@eecs.umich.edu{ 1655643Sgblack@eecs.umich.edu protected: 1665643Sgblack@eecs.umich.edu const ExtMachInst _inst; 1675643Sgblack@eecs.umich.edu 1685643Sgblack@eecs.umich.edu public: 1695643Sgblack@eecs.umich.edu InstFault(FaultName n, const ExtMachInst inst) 1705643Sgblack@eecs.umich.edu : RiscvFault(n, false, INST_ILLEGAL), _inst(inst) 1715643Sgblack@eecs.umich.edu {} 1725643Sgblack@eecs.umich.edu 1735643Sgblack@eecs.umich.edu MiscReg trap_value() const override { return _inst; } 1745643Sgblack@eecs.umich.edu}; 1755643Sgblack@eecs.umich.edu 1765643Sgblack@eecs.umich.educlass UnknownInstFault : public InstFault 1775643Sgblack@eecs.umich.edu{ 1785643Sgblack@eecs.umich.edu public: 1795643Sgblack@eecs.umich.edu UnknownInstFault(const ExtMachInst inst) 1805643Sgblack@eecs.umich.edu : InstFault("Unknown instruction", inst) 1815643Sgblack@eecs.umich.edu {} 1825643Sgblack@eecs.umich.edu 1835643Sgblack@eecs.umich.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 1845643Sgblack@eecs.umich.edu}; 1855643Sgblack@eecs.umich.edu 1865643Sgblack@eecs.umich.educlass IllegalInstFault : public InstFault 1875643Sgblack@eecs.umich.edu{ 1885643Sgblack@eecs.umich.edu private: 1895643Sgblack@eecs.umich.edu const std::string reason; 1905643Sgblack@eecs.umich.edu 1915643Sgblack@eecs.umich.edu public: 1925643Sgblack@eecs.umich.edu IllegalInstFault(std::string r, const ExtMachInst inst) 1935643Sgblack@eecs.umich.edu : InstFault("Illegal instruction", inst) 1945643Sgblack@eecs.umich.edu {} 1955643Sgblack@eecs.umich.edu 1965643Sgblack@eecs.umich.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 1975643Sgblack@eecs.umich.edu}; 1986712Snate@binkert.org 1995651Sgblack@eecs.umich.educlass UnimplementedFault : public InstFault 2005657Sgblack@eecs.umich.edu{ 2015657Sgblack@eecs.umich.edu private: 2025657Sgblack@eecs.umich.edu const std::string instName; 2035657Sgblack@eecs.umich.edu 2045657Sgblack@eecs.umich.edu public: 2055657Sgblack@eecs.umich.edu UnimplementedFault(std::string name, const ExtMachInst inst) 2065651Sgblack@eecs.umich.edu : InstFault("Unimplemented instruction", inst), 2075651Sgblack@eecs.umich.edu instName(name) 2085654Sgblack@eecs.umich.edu {} 2095654Sgblack@eecs.umich.edu 2106138Sgblack@eecs.umich.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 2116138Sgblack@eecs.umich.edu}; 2126138Sgblack@eecs.umich.edu 2136138Sgblack@eecs.umich.educlass IllegalFrmFault: public InstFault 2146138Sgblack@eecs.umich.edu{ 2156138Sgblack@eecs.umich.edu private: 2166138Sgblack@eecs.umich.edu const uint8_t frm; 2176138Sgblack@eecs.umich.edu 2186138Sgblack@eecs.umich.edu public: 2196138Sgblack@eecs.umich.edu IllegalFrmFault(uint8_t r, const ExtMachInst inst) 2206138Sgblack@eecs.umich.edu : InstFault("Illegal floating-point rounding mode", inst), 2216138Sgblack@eecs.umich.edu frm(r) 2226138Sgblack@eecs.umich.edu {} 2236138Sgblack@eecs.umich.edu 2246138Sgblack@eecs.umich.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 2256138Sgblack@eecs.umich.edu}; 2266138Sgblack@eecs.umich.edu 2278746Sgblack@eecs.umich.educlass AddressFault : public RiscvFault 22811150Smitch.hayenga@arm.com{ 2296138Sgblack@eecs.umich.edu private: 2306138Sgblack@eecs.umich.edu const Addr _addr; 2318746Sgblack@eecs.umich.edu 2326138Sgblack@eecs.umich.edu public: 2336138Sgblack@eecs.umich.edu AddressFault(const Addr addr, ExceptionCode code) 2346139Sgblack@eecs.umich.edu : RiscvFault("Address", false, code), _addr(addr) 2356139Sgblack@eecs.umich.edu {} 2366139Sgblack@eecs.umich.edu 2376139Sgblack@eecs.umich.edu MiscReg trap_value() const override { return _addr; } 2386139Sgblack@eecs.umich.edu}; 2396139Sgblack@eecs.umich.edu 2406139Sgblack@eecs.umich.educlass BreakpointFault : public RiscvFault 2416139Sgblack@eecs.umich.edu{ 2426139Sgblack@eecs.umich.edu private: 2436139Sgblack@eecs.umich.edu const PCState pcState; 2446139Sgblack@eecs.umich.edu 2456139Sgblack@eecs.umich.edu public: 2466139Sgblack@eecs.umich.edu BreakpointFault(const PCState &pc) 2476139Sgblack@eecs.umich.edu : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc) 2486139Sgblack@eecs.umich.edu {} 2496139Sgblack@eecs.umich.edu 2506138Sgblack@eecs.umich.edu MiscReg trap_value() const override { return pcState.pc(); } 2516138Sgblack@eecs.umich.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 2529524SAndreas.Sandberg@ARM.com}; 2535643Sgblack@eecs.umich.edu 2545643Sgblack@eecs.umich.educlass SyscallFault : public RiscvFault 2555643Sgblack@eecs.umich.edu{ 2565827Sgblack@eecs.umich.edu public: 2575827Sgblack@eecs.umich.edu // TODO: replace ECALL_USER with the appropriate privilege level of the 2585827Sgblack@eecs.umich.edu // caller 2595827Sgblack@eecs.umich.edu SyscallFault() : RiscvFault("System call", false, ECALL_USER) {} 2605827Sgblack@eecs.umich.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 2615827Sgblack@eecs.umich.edu}; 2625827Sgblack@eecs.umich.edu 2635827Sgblack@eecs.umich.edu} // namespace RiscvISA 2645827Sgblack@eecs.umich.edu 2655827Sgblack@eecs.umich.edu#endif // __ARCH_RISCV_FAULTS_HH__