faults.cc revision 12136:1070125670e2
12SN/A/* 21762SN/A * Copyright (c) 2016 RISC-V Foundation 32SN/A * Copyright (c) 2016 The University of Virginia 42SN/A * All rights reserved. 52SN/A * 62SN/A * Redistribution and use in source and binary forms, with or without 72SN/A * modification, are permitted provided that the following conditions are 82SN/A * met: redistributions of source code must retain the above copyright 92SN/A * notice, this list of conditions and the following disclaimer; 102SN/A * redistributions in binary form must reproduce the above copyright 112SN/A * notice, this list of conditions and the following disclaimer in the 122SN/A * documentation and/or other materials provided with the distribution; 132SN/A * neither the name of the copyright holders nor the names of its 142SN/A * contributors may be used to endorse or promote products derived from 152SN/A * this software without specific prior written permission. 162SN/A * 172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Alec Roelke 302SN/A */ 312SN/A#include "arch/riscv/faults.hh" 322SN/A 332SN/A#include "arch/riscv/utility.hh" 348229Snate@binkert.org#include "cpu/thread_context.hh" 352SN/A#include "sim/debug.hh" 362SN/A#include "sim/full_system.hh" 3756SN/A 3856SN/Ausing namespace RiscvISA; 392SN/A 402SN/Avoid 412SN/ARiscvFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 422SN/A{ 432SN/A panic("Fault %s encountered at pc 0x%016llx.", name(), tc->pcState().pc()); 442SN/A} 452SN/A 462SN/Avoid 47160SN/ARiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 48160SN/A{ 492SN/A if (FullSystem) { 502SN/A panic("Full system mode not supported for RISC-V."); 512SN/A } else { 522SN/A invoke_se(tc, inst); 532SN/A PCState pcState = tc->pcState(); 542SN/A advancePC(pcState, inst); 552SN/A tc->pcState(pcState); 562SN/A } 572SN/A} 582SN/A 592SN/Avoid 602SN/AUnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 612SN/A{ 622SN/A panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst, 632SN/A tc->pcState().pc()); 642SN/A} 652SN/A 662SN/Avoid 672SN/AIllegalInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 682SN/A{ 692SN/A panic("Illegal instruction 0x%08x at pc 0x%016llx: %s", inst->machInst, 702SN/A tc->pcState().pc(), reason.c_str()); 712SN/A} 722SN/A 732SN/Avoid 742SN/AUnimplementedFault::invoke_se(ThreadContext *tc, 752SN/A const StaticInstPtr &inst) 762SN/A{ 772SN/A panic("Unimplemented instruction %s at pc 0x%016llx", instName, 78160SN/A tc->pcState().pc()); 79160SN/A} 802SN/A 812SN/Avoid 822SN/AIllegalFrmFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 832SN/A{ 842SN/A panic("Illegal floating-point rounding mode 0x%x at pc 0x%016llx.", 852SN/A frm, tc->pcState().pc()); 862SN/A} 87160SN/A 88160SN/Avoid 89160SN/ABreakpointFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 90160SN/A{ 912SN/A schedRelBreak(0); 922SN/A} 932SN/A 942SN/Avoid 952SN/ASyscallFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 962SN/A{ 972SN/A Fault *fault = NoFault; 98160SN/A tc->syscall(tc->readIntReg(SyscallNumReg), fault); 99160SN/A} 100160SN/A