faults.cc revision 11877:5ea85692a53e
17119Sgblack@eecs.umich.edu/* 27119Sgblack@eecs.umich.edu * Copyright (c) 2016 RISC-V Foundation 312110SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2016 The University of Virginia 47120Sgblack@eecs.umich.edu * All rights reserved. 57120Sgblack@eecs.umich.edu * 67120Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 77120Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 87120Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 97120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 107120Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 117120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 127120Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 137120Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 147120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 157119Sgblack@eecs.umich.edu * this software without specific prior written permission. 167119Sgblack@eecs.umich.edu * 177119Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 187119Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 197119Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 207119Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 217119Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 227119Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 237119Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 247119Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 257119Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 267119Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 277119Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 287119Sgblack@eecs.umich.edu * 297119Sgblack@eecs.umich.edu * Authors: Alec Roelke 307119Sgblack@eecs.umich.edu */ 317119Sgblack@eecs.umich.edu#include "arch/riscv/faults.hh" 327119Sgblack@eecs.umich.edu 337119Sgblack@eecs.umich.edu#include "arch/riscv/utility.hh" 347119Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 357119Sgblack@eecs.umich.edu#include "sim/debug.hh" 367119Sgblack@eecs.umich.edu#include "sim/full_system.hh" 377119Sgblack@eecs.umich.edu 387119Sgblack@eecs.umich.eduusing namespace RiscvISA; 397119Sgblack@eecs.umich.edu 407119Sgblack@eecs.umich.eduvoid 417119Sgblack@eecs.umich.eduRiscvFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 427119Sgblack@eecs.umich.edu{ 437119Sgblack@eecs.umich.edu panic("Fault %s encountered at pc 0x%016llx.", name(), tc->pcState().pc()); 447646Sgene.wu@arm.com} 4512234Sgabeblack@google.com 467646Sgene.wu@arm.comvoid 477646Sgene.wu@arm.comRiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 487646Sgene.wu@arm.com{ 497646Sgene.wu@arm.com if (FullSystem) { 507646Sgene.wu@arm.com panic("Full system mode not supported for RISC-V."); 517646Sgene.wu@arm.com } else { 527646Sgene.wu@arm.com invoke_se(tc, inst); 537646Sgene.wu@arm.com PCState pcState = tc->pcState(); 5412234Sgabeblack@google.com advancePC(pcState, inst); 557646Sgene.wu@arm.com tc->pcState(pcState); 567646Sgene.wu@arm.com } 577646Sgene.wu@arm.com} 587646Sgene.wu@arm.com 597646Sgene.wu@arm.comvoid 607646Sgene.wu@arm.comUnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 617646Sgene.wu@arm.com{ 627646Sgene.wu@arm.com panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst, 6312234Sgabeblack@google.com tc->pcState().pc()); 647646Sgene.wu@arm.com} 657646Sgene.wu@arm.com 667646Sgene.wu@arm.comvoid 677646Sgene.wu@arm.comUnimplementedFault::invoke_se(ThreadContext *tc, 687646Sgene.wu@arm.com const StaticInstPtr &inst) 697646Sgene.wu@arm.com{ 707646Sgene.wu@arm.com panic("Unimplemented instruction %s at pc 0x%016llx", instName, 717646Sgene.wu@arm.com tc->pcState().pc()); 727205Sgblack@eecs.umich.edu} 7312234Sgabeblack@google.com 747205Sgblack@eecs.umich.eduvoid 757205Sgblack@eecs.umich.eduIllegalFrmFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 767205Sgblack@eecs.umich.edu{ 777205Sgblack@eecs.umich.edu panic("Illegal floating-point rounding mode 0x%x at pc 0x%016llx.", 787205Sgblack@eecs.umich.edu frm, tc->pcState().pc()); 797205Sgblack@eecs.umich.edu} 807205Sgblack@eecs.umich.edu 817205Sgblack@eecs.umich.eduvoid 827205Sgblack@eecs.umich.eduBreakpointFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 837205Sgblack@eecs.umich.edu{ 847205Sgblack@eecs.umich.edu schedRelBreak(0); 857205Sgblack@eecs.umich.edu} 867205Sgblack@eecs.umich.edu 877205Sgblack@eecs.umich.eduvoid 887205Sgblack@eecs.umich.eduSyscallFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 898442Sgblack@eecs.umich.edu{ 908442Sgblack@eecs.umich.edu Fault *fault = NoFault; 917205Sgblack@eecs.umich.edu tc->syscall(tc->readIntReg(SyscallNumReg), fault); 927205Sgblack@eecs.umich.edu} 937205Sgblack@eecs.umich.edu