faults.cc revision 11723:0596db108c53 
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31#include "arch/riscv/faults.hh"
32
33#include "arch/riscv/utility.hh"
34#include "cpu/thread_context.hh"
35#include "sim/debug.hh"
36#include "sim/full_system.hh"
37
38using namespace RiscvISA;
39
40void
41RiscvFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
42{
43    panic("Fault %s encountered at pc 0x%016llx.", name(), tc->pcState().pc());
44}
45
46void
47RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
48{
49    if (FullSystem) {
50        panic("Full system mode not supported for RISC-V.");
51    } else {
52        invoke_se(tc, inst);
53        PCState pcState = tc->pcState();
54        advancePC(pcState, inst);
55        tc->pcState(pcState);
56    }
57}
58
59void
60UnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
61{
62    panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst,
63        tc->pcState().pc());
64}
65
66void
67UnimplementedFault::invoke_se(ThreadContext *tc,
68        const StaticInstPtr &inst)
69{
70    panic("Unimplemented instruction %s at pc 0x%016llx", instName,
71        tc->pcState().pc());
72}
73
74void
75BreakpointFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
76{
77    schedRelBreak(0);
78}
79
80void
81SyscallFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
82{
83    tc->syscall(tc->readIntReg(SyscallNumReg));
84}
85