faults.cc revision 13547
111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2016 RISC-V Foundation 311723Sar4jc@virginia.edu * Copyright (c) 2016 The University of Virginia 412808Srobert.scheffel1@tu-dresden.de * Copyright (c) 2018 TU Dresden 511723Sar4jc@virginia.edu * All rights reserved. 611723Sar4jc@virginia.edu * 711723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 811723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 911723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 1011723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 1111723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1211723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1311723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1411723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1511723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1611723Sar4jc@virginia.edu * this software without specific prior written permission. 1711723Sar4jc@virginia.edu * 1811723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1911723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2011723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2111723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2211723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2311723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2411723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2511723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2611723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2711723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2811723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2911723Sar4jc@virginia.edu * 3011723Sar4jc@virginia.edu * Authors: Alec Roelke 3112808Srobert.scheffel1@tu-dresden.de * Robert Scheffel 3211723Sar4jc@virginia.edu */ 3311723Sar4jc@virginia.edu#include "arch/riscv/faults.hh" 3411723Sar4jc@virginia.edu 3512848Sar4jc@virginia.edu#include "arch/riscv/isa.hh" 3612848Sar4jc@virginia.edu#include "arch/riscv/registers.hh" 3712808Srobert.scheffel1@tu-dresden.de#include "arch/riscv/system.hh" 3811723Sar4jc@virginia.edu#include "arch/riscv/utility.hh" 3912808Srobert.scheffel1@tu-dresden.de#include "cpu/base.hh" 4011723Sar4jc@virginia.edu#include "cpu/thread_context.hh" 4111723Sar4jc@virginia.edu#include "sim/debug.hh" 4211723Sar4jc@virginia.edu#include "sim/full_system.hh" 4311723Sar4jc@virginia.edu 4412848Sar4jc@virginia.edunamespace RiscvISA 4512848Sar4jc@virginia.edu{ 4611723Sar4jc@virginia.edu 4711723Sar4jc@virginia.eduvoid 4812848Sar4jc@virginia.eduRiscvFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) 4911723Sar4jc@virginia.edu{ 5011723Sar4jc@virginia.edu panic("Fault %s encountered at pc 0x%016llx.", name(), tc->pcState().pc()); 5111723Sar4jc@virginia.edu} 5211723Sar4jc@virginia.edu 5311723Sar4jc@virginia.eduvoid 5411723Sar4jc@virginia.eduRiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 5511723Sar4jc@virginia.edu{ 5612848Sar4jc@virginia.edu PCState pcState = tc->pcState(); 5712848Sar4jc@virginia.edu 5811723Sar4jc@virginia.edu if (FullSystem) { 5912848Sar4jc@virginia.edu PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV); 6012848Sar4jc@virginia.edu PrivilegeMode prv = PRV_M; 6112848Sar4jc@virginia.edu STATUS status = tc->readMiscReg(MISCREG_STATUS); 6212848Sar4jc@virginia.edu 6312848Sar4jc@virginia.edu // Set fault handler privilege mode 6412848Sar4jc@virginia.edu if (pp != PRV_M && 6512848Sar4jc@virginia.edu bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) { 6612848Sar4jc@virginia.edu prv = PRV_S; 6712848Sar4jc@virginia.edu } 6812848Sar4jc@virginia.edu if (pp == PRV_U && 6912848Sar4jc@virginia.edu bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) { 7012848Sar4jc@virginia.edu prv = PRV_U; 7112848Sar4jc@virginia.edu } 7212848Sar4jc@virginia.edu 7312848Sar4jc@virginia.edu // Set fault registers and status 7412849Sar4jc@virginia.edu MiscRegIndex cause, epc, tvec, tval; 7512848Sar4jc@virginia.edu switch (prv) { 7612848Sar4jc@virginia.edu case PRV_U: 7712848Sar4jc@virginia.edu cause = MISCREG_UCAUSE; 7812848Sar4jc@virginia.edu epc = MISCREG_UEPC; 7912848Sar4jc@virginia.edu tvec = MISCREG_UTVEC; 8012849Sar4jc@virginia.edu tval = MISCREG_UTVAL; 8112848Sar4jc@virginia.edu 8212848Sar4jc@virginia.edu status.upie = status.uie; 8312848Sar4jc@virginia.edu status.uie = 0; 8412848Sar4jc@virginia.edu break; 8512848Sar4jc@virginia.edu case PRV_S: 8612848Sar4jc@virginia.edu cause = MISCREG_SCAUSE; 8712848Sar4jc@virginia.edu epc = MISCREG_SEPC; 8812848Sar4jc@virginia.edu tvec = MISCREG_STVEC; 8912849Sar4jc@virginia.edu tval = MISCREG_STVAL; 9012848Sar4jc@virginia.edu 9112848Sar4jc@virginia.edu status.spp = pp; 9212848Sar4jc@virginia.edu status.spie = status.sie; 9312848Sar4jc@virginia.edu status.sie = 0; 9412848Sar4jc@virginia.edu break; 9512848Sar4jc@virginia.edu case PRV_M: 9612848Sar4jc@virginia.edu cause = MISCREG_MCAUSE; 9712848Sar4jc@virginia.edu epc = MISCREG_MEPC; 9812848Sar4jc@virginia.edu tvec = MISCREG_MTVEC; 9912849Sar4jc@virginia.edu tval = MISCREG_MTVAL; 10012848Sar4jc@virginia.edu 10112848Sar4jc@virginia.edu status.mpp = pp; 10212848Sar4jc@virginia.edu status.mpie = status.sie; 10312848Sar4jc@virginia.edu status.mie = 0; 10412848Sar4jc@virginia.edu break; 10512848Sar4jc@virginia.edu default: 10612848Sar4jc@virginia.edu panic("Unknown privilege mode %d.", prv); 10712848Sar4jc@virginia.edu break; 10812848Sar4jc@virginia.edu } 10912848Sar4jc@virginia.edu 11012848Sar4jc@virginia.edu // Set fault cause, privilege, and return PC 11112848Sar4jc@virginia.edu tc->setMiscReg(cause, 11212848Sar4jc@virginia.edu (isInterrupt() << (sizeof(MiscReg) * 4 - 1)) | _code); 11312848Sar4jc@virginia.edu tc->setMiscReg(epc, tc->instAddr()); 11412849Sar4jc@virginia.edu tc->setMiscReg(tval, trap_value()); 11512848Sar4jc@virginia.edu tc->setMiscReg(MISCREG_PRV, prv); 11612848Sar4jc@virginia.edu tc->setMiscReg(MISCREG_STATUS, status); 11712848Sar4jc@virginia.edu 11812848Sar4jc@virginia.edu // Set PC to fault handler address 11912848Sar4jc@virginia.edu pcState.set(tc->readMiscReg(tvec) >> 2); 12011723Sar4jc@virginia.edu } else { 12112848Sar4jc@virginia.edu invokeSE(tc, inst); 12211723Sar4jc@virginia.edu advancePC(pcState, inst); 12311723Sar4jc@virginia.edu } 12412848Sar4jc@virginia.edu tc->pcState(pcState); 12511723Sar4jc@virginia.edu} 12611723Sar4jc@virginia.edu 12712808Srobert.scheffel1@tu-dresden.devoid Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 12812808Srobert.scheffel1@tu-dresden.de{ 12912808Srobert.scheffel1@tu-dresden.de if (FullSystem) { 13012808Srobert.scheffel1@tu-dresden.de tc->getCpuPtr()->clearInterrupts(tc->threadId()); 13112808Srobert.scheffel1@tu-dresden.de tc->clearArchRegs(); 13212808Srobert.scheffel1@tu-dresden.de } 13312808Srobert.scheffel1@tu-dresden.de 13413547Sar4jc@virginia.edu tc->setMiscReg(MISCREG_PRV, PRV_M); 13513547Sar4jc@virginia.edu STATUS status = tc->readMiscReg(MISCREG_STATUS); 13613547Sar4jc@virginia.edu status.mie = 0; 13713547Sar4jc@virginia.edu status.mprv = 0; 13813547Sar4jc@virginia.edu tc->setMiscReg(MISCREG_STATUS, status); 13913547Sar4jc@virginia.edu tc->setMiscReg(MISCREG_MCAUSE, 0); 14013547Sar4jc@virginia.edu 14112808Srobert.scheffel1@tu-dresden.de // Advance the PC to the implementation-defined reset vector 14212808Srobert.scheffel1@tu-dresden.de PCState pc = static_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect(); 14312808Srobert.scheffel1@tu-dresden.de tc->pcState(pc); 14412808Srobert.scheffel1@tu-dresden.de} 14512808Srobert.scheffel1@tu-dresden.de 14611723Sar4jc@virginia.eduvoid 14712848Sar4jc@virginia.eduUnknownInstFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) 14811723Sar4jc@virginia.edu{ 14911723Sar4jc@virginia.edu panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst, 15011723Sar4jc@virginia.edu tc->pcState().pc()); 15111723Sar4jc@virginia.edu} 15211723Sar4jc@virginia.edu 15311723Sar4jc@virginia.eduvoid 15412848Sar4jc@virginia.eduIllegalInstFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) 15512136Sar4jc@virginia.edu{ 15612136Sar4jc@virginia.edu panic("Illegal instruction 0x%08x at pc 0x%016llx: %s", inst->machInst, 15712136Sar4jc@virginia.edu tc->pcState().pc(), reason.c_str()); 15812136Sar4jc@virginia.edu} 15912136Sar4jc@virginia.edu 16012136Sar4jc@virginia.eduvoid 16112848Sar4jc@virginia.eduUnimplementedFault::invokeSE(ThreadContext *tc, 16211723Sar4jc@virginia.edu const StaticInstPtr &inst) 16311723Sar4jc@virginia.edu{ 16411723Sar4jc@virginia.edu panic("Unimplemented instruction %s at pc 0x%016llx", instName, 16511723Sar4jc@virginia.edu tc->pcState().pc()); 16611723Sar4jc@virginia.edu} 16711723Sar4jc@virginia.edu 16811723Sar4jc@virginia.eduvoid 16912848Sar4jc@virginia.eduIllegalFrmFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) 17011725Sar4jc@virginia.edu{ 17111725Sar4jc@virginia.edu panic("Illegal floating-point rounding mode 0x%x at pc 0x%016llx.", 17211725Sar4jc@virginia.edu frm, tc->pcState().pc()); 17311725Sar4jc@virginia.edu} 17411725Sar4jc@virginia.edu 17511725Sar4jc@virginia.eduvoid 17612848Sar4jc@virginia.eduBreakpointFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) 17711723Sar4jc@virginia.edu{ 17811723Sar4jc@virginia.edu schedRelBreak(0); 17911723Sar4jc@virginia.edu} 18011723Sar4jc@virginia.edu 18111723Sar4jc@virginia.eduvoid 18212848Sar4jc@virginia.eduSyscallFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) 18311723Sar4jc@virginia.edu{ 18411877Sbrandon.potter@amd.com Fault *fault = NoFault; 18511877Sbrandon.potter@amd.com tc->syscall(tc->readIntReg(SyscallNumReg), fault); 18611723Sar4jc@virginia.edu} 18712848Sar4jc@virginia.edu 18812848Sar4jc@virginia.edu} // namespace RiscvISA