utility.cc revision 12334
13536Sgblack@eecs.umich.edu/*
23536Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan
33536Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University
43536Sgblack@eecs.umich.edu * Copyright (c) 2009 The University of Edinburgh
53536Sgblack@eecs.umich.edu * All rights reserved.
63536Sgblack@eecs.umich.edu *
73536Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
83536Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
93536Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
103536Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
113536Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
123536Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
133536Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution;
143536Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its
153536Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
163536Sgblack@eecs.umich.edu * this software without specific prior written permission.
173536Sgblack@eecs.umich.edu *
183536Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
193536Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
203536Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
213536Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
223536Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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243536Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
253536Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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273536Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
283536Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
293536Sgblack@eecs.umich.edu *
303536Sgblack@eecs.umich.edu * Authors: Korey Sewell
313536Sgblack@eecs.umich.edu *          Stephen Hines
328332Snate@binkert.org *          Timothy M. Jones
338332Snate@binkert.org */
343536Sgblack@eecs.umich.edu
353536Sgblack@eecs.umich.edu#include "arch/power/utility.hh"
363536Sgblack@eecs.umich.edu
373536Sgblack@eecs.umich.edu#include "base/logging.hh"
383536Sgblack@eecs.umich.edu
393536Sgblack@eecs.umich.edunamespace PowerISA {
403536Sgblack@eecs.umich.edu
415543Ssaidi@eecs.umich.eduvoid
425543Ssaidi@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest)
433536Sgblack@eecs.umich.edu{
443536Sgblack@eecs.umich.edu    // First loop through the integer registers.
453536Sgblack@eecs.umich.edu    for (int i = 0; i < NumIntRegs; ++i)
463536Sgblack@eecs.umich.edu        dest->setIntReg(i, src->readIntReg(i));
473536Sgblack@eecs.umich.edu
483536Sgblack@eecs.umich.edu    // Then loop through the floating point registers.
493536Sgblack@eecs.umich.edu    for (int i = 0; i < NumFloatRegs; ++i)
503536Sgblack@eecs.umich.edu        dest->setFloatRegBits(i, src->readFloatRegBits(i));
513536Sgblack@eecs.umich.edu
523536Sgblack@eecs.umich.edu    // Would need to add condition-code regs if implemented
533536Sgblack@eecs.umich.edu    assert(NumCCRegs == 0);
545543Ssaidi@eecs.umich.edu
555543Ssaidi@eecs.umich.edu    // Copy misc. registers
563536Sgblack@eecs.umich.edu    copyMiscRegs(src, dest);
573536Sgblack@eecs.umich.edu
583536Sgblack@eecs.umich.edu    // Lastly copy PC/NPC
593536Sgblack@eecs.umich.edu    dest->pcState(src->pcState());
603536Sgblack@eecs.umich.edu}
613536Sgblack@eecs.umich.edu
623536Sgblack@eecs.umich.eduuint64_t
633536Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
643536Sgblack@eecs.umich.edu{
653536Sgblack@eecs.umich.edu    panic("getArgument not implemented for POWER.\n");
663536Sgblack@eecs.umich.edu    return 0;
673536Sgblack@eecs.umich.edu}
683536Sgblack@eecs.umich.edu
693536Sgblack@eecs.umich.eduvoid
703536Sgblack@eecs.umich.eduskipFunction(ThreadContext *tc)
713536Sgblack@eecs.umich.edu{
725543Ssaidi@eecs.umich.edu    panic("Not Implemented for POWER");
733536Sgblack@eecs.umich.edu}
743536Sgblack@eecs.umich.edu
753536Sgblack@eecs.umich.eduvoid
763536Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId)
773536Sgblack@eecs.umich.edu{
783536Sgblack@eecs.umich.edu    panic("initCPU not implemented for POWER.\n");
793536Sgblack@eecs.umich.edu}
803536Sgblack@eecs.umich.edu
813536Sgblack@eecs.umich.edu
823536Sgblack@eecs.umich.edu} // namespace PowerISA
833536Sgblack@eecs.umich.edu