utility.cc revision 11793:ef606668d247
110802Srene.dejong@arm.com/*
210802Srene.dejong@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan
310802Srene.dejong@arm.com * Copyright (c) 2007-2008 The Florida State University
410802Srene.dejong@arm.com * Copyright (c) 2009 The University of Edinburgh
510802Srene.dejong@arm.com * All rights reserved.
610802Srene.dejong@arm.com *
710802Srene.dejong@arm.com * Redistribution and use in source and binary forms, with or without
810802Srene.dejong@arm.com * modification, are permitted provided that the following conditions are
910802Srene.dejong@arm.com * met: redistributions of source code must retain the above copyright
1010802Srene.dejong@arm.com * notice, this list of conditions and the following disclaimer;
1110802Srene.dejong@arm.com * redistributions in binary form must reproduce the above copyright
1210802Srene.dejong@arm.com * notice, this list of conditions and the following disclaimer in the
1310802Srene.dejong@arm.com * documentation and/or other materials provided with the distribution;
1410802Srene.dejong@arm.com * neither the name of the copyright holders nor the names of its
1510802Srene.dejong@arm.com * contributors may be used to endorse or promote products derived from
1610802Srene.dejong@arm.com * this software without specific prior written permission.
1710802Srene.dejong@arm.com *
1810802Srene.dejong@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1910802Srene.dejong@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
2010802Srene.dejong@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2110802Srene.dejong@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2210802Srene.dejong@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2310802Srene.dejong@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2410802Srene.dejong@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2510802Srene.dejong@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2610802Srene.dejong@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2710802Srene.dejong@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2810802Srene.dejong@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2910802Srene.dejong@arm.com *
3010802Srene.dejong@arm.com * Authors: Korey Sewell
3110802Srene.dejong@arm.com *          Stephen Hines
3210802Srene.dejong@arm.com *          Timothy M. Jones
3310802Srene.dejong@arm.com */
3410802Srene.dejong@arm.com
3510802Srene.dejong@arm.com#include "arch/power/utility.hh"
3610802Srene.dejong@arm.com
3710802Srene.dejong@arm.com#include "base/misc.hh"
3810802Srene.dejong@arm.com
3910802Srene.dejong@arm.comnamespace PowerISA {
4010802Srene.dejong@arm.com
4110802Srene.dejong@arm.comvoid
4210802Srene.dejong@arm.comcopyRegs(ThreadContext *src, ThreadContext *dest)
4310802Srene.dejong@arm.com{
4410802Srene.dejong@arm.com    // First loop through the integer registers.
4510802Srene.dejong@arm.com    for (int i = 0; i < NumIntRegs; ++i)
4610802Srene.dejong@arm.com        dest->setIntReg(i, src->readIntReg(i));
4710802Srene.dejong@arm.com
4810802Srene.dejong@arm.com    // Then loop through the floating point registers.
4910802Srene.dejong@arm.com    for (int i = 0; i < NumFloatRegs; ++i)
5010802Srene.dejong@arm.com        dest->setFloatRegBits(i, src->readFloatRegBits(i));
5110802Srene.dejong@arm.com
5210802Srene.dejong@arm.com    // Would need to add condition-code regs if implemented
5310802Srene.dejong@arm.com    assert(NumCCRegs == 0);
5410802Srene.dejong@arm.com
5510802Srene.dejong@arm.com    // Copy misc. registers
5610802Srene.dejong@arm.com    copyMiscRegs(src, dest);
5710802Srene.dejong@arm.com
5810802Srene.dejong@arm.com    // Lastly copy PC/NPC
5910802Srene.dejong@arm.com    dest->pcState(src->pcState());
6010802Srene.dejong@arm.com}
6110802Srene.dejong@arm.com
6210802Srene.dejong@arm.comuint64_t
6310802Srene.dejong@arm.comgetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
6410802Srene.dejong@arm.com{
6510802Srene.dejong@arm.com    panic("getArgument not implemented for POWER.\n");
6610802Srene.dejong@arm.com    return 0;
6710802Srene.dejong@arm.com}
6810802Srene.dejong@arm.com
6910802Srene.dejong@arm.comvoid
7010802Srene.dejong@arm.comskipFunction(ThreadContext *tc)
7110802Srene.dejong@arm.com{
7210802Srene.dejong@arm.com    panic("Not Implemented for POWER");
7310802Srene.dejong@arm.com}
7410802Srene.dejong@arm.com
7510802Srene.dejong@arm.comvoid
7610802Srene.dejong@arm.cominitCPU(ThreadContext *tc, int cpuId)
7710802Srene.dejong@arm.com{
7810802Srene.dejong@arm.com    panic("initCPU not implemented for POWER.\n");
7910802Srene.dejong@arm.com}
8010802Srene.dejong@arm.com
8110802Srene.dejong@arm.com
8210802Srene.dejong@arm.com} // namespace PowerISA
8310802Srene.dejong@arm.com