registers.hh revision 12109:f29e9c5418aa 
1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Timothy M. Jones
29 */
30
31#ifndef __ARCH_POWER_REGISTERS_HH__
32#define __ARCH_POWER_REGISTERS_HH__
33
34#include "arch/generic/vec_reg.hh"
35#include "arch/power/generated/max_inst_regs.hh"
36#include "arch/power/miscregs.hh"
37
38namespace PowerISA {
39
40using PowerISAInst::MaxInstSrcRegs;
41using PowerISAInst::MaxInstDestRegs;
42
43// Power writes a misc register outside of the isa parser, so it can't
44// be detected by it. Manually add it here.
45const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
46
47typedef uint64_t IntReg;
48
49// Floating point register file entry type
50typedef uint64_t FloatRegBits;
51typedef double FloatReg;
52typedef uint64_t MiscReg;
53
54// dummy typedef since we don't have CC regs
55typedef uint8_t CCReg;
56
57// dummy typedefs since we don't have vector regs
58constexpr unsigned NumVecElemPerVecReg = 2;
59using VecElem = uint32_t;
60using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
61using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
62using VecRegContainer = VecReg::Container;
63// This has to be one to prevent warnings that are treated as errors
64constexpr unsigned NumVecRegs = 1;
65
66// Constants Related to the number of registers
67const int NumIntArchRegs = 32;
68
69// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
70// and zero register, which doesn't actually exist but needs a number
71const int NumIntSpecialRegs = 9;
72const int NumFloatArchRegs = 32;
73const int NumFloatSpecialRegs = 0;
74const int NumInternalProcRegs = 0;
75
76const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
77const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
78const int NumCCRegs = 0;
79const int NumMiscRegs = NUM_MISCREGS;
80
81// Semantically meaningful register indices
82const int ReturnValueReg = 3;
83const int ArgumentReg0 = 3;
84const int ArgumentReg1 = 4;
85const int ArgumentReg2 = 5;
86const int ArgumentReg3 = 6;
87const int ArgumentReg4 = 7;
88const int FramePointerReg = 31;
89const int StackPointerReg = 1;
90
91// There isn't one in Power, but we need to define one somewhere
92const int ZeroReg = NumIntRegs - 1;
93
94const int SyscallNumReg = 0;
95const int SyscallPseudoReturnReg = 3;
96const int SyscallSuccessReg = 3;
97
98typedef union {
99    IntReg   intreg;
100    FloatReg fpreg;
101    MiscReg  ctrlreg;
102} AnyReg;
103
104enum MiscIntRegNums {
105    INTREG_CR = NumIntArchRegs,
106    INTREG_XER,
107    INTREG_LR,
108    INTREG_CTR,
109    INTREG_FPSCR,
110    INTREG_RSV,
111    INTREG_RSV_LEN,
112    INTREG_RSV_ADDR
113};
114
115} // namespace PowerISA
116
117#endif // __ARCH_POWER_REGISTERS_HH__
118