pagetable.hh revision 6691 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Authors: Nathan Binkert
32 *          Steve Reinhardt
33 *          Jaidev Patwardhan
34 *          Stephen Hines
35 *          Timothy M. Jones
36 */
37
38#ifndef __ARCH_POWER_PAGETABLE_H__
39#define __ARCH_POWER_PAGETABLE_H__
40
41#include "arch/power/isa_traits.hh"
42#include "arch/power/utility.hh"
43#include "arch/power/vtophys.hh"
44#include "config/full_system.hh"
45
46namespace PowerISA {
47
48struct VAddr
49{
50    static const int ImplBits = 43;
51    static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
52    static const Addr UnImplMask = ~ImplMask;
53
54    Addr addr;
55
56    VAddr(Addr a)
57        : addr(a)
58    {}
59
60    operator Addr() const
61    {
62        return addr;
63    }
64
65    const VAddr
66    &operator=(Addr a)
67    {
68        addr = a;
69        return *this;
70    }
71
72    Addr
73    vpn() const
74    {
75        return (addr & ImplMask) >> PageShift;
76    }
77
78    Addr
79    page() const
80    {
81        return addr & Page_Mask;
82    }
83
84    Addr
85    offset() const
86    {
87        return addr & PageOffset;
88    }
89
90    Addr
91    level3() const
92    {
93        return PowerISA::PteAddr(addr >> PageShift);
94    }
95
96    Addr
97    level2() const
98    {
99        return PowerISA::PteAddr(addr >> (NPtePageShift + PageShift));
100    }
101
102    Addr
103    level1() const
104    {
105        return PowerISA::PteAddr(addr >> (2 * NPtePageShift + PageShift));
106    }
107};
108
109// ITB/DTB page table entry
110struct PTE
111{
112    // What parts of the VAddr (from bits 28..11) should be used in
113    // translation (includes Mask and MaskX from PageMask)
114    Addr Mask;
115
116    // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11
117    // from EntryHi)
118    Addr VPN;
119
120    // Address Space ID (8 bits) // Lower 8 bits of EntryHi
121    uint8_t asid;
122
123    // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
124    bool G;
125
126    /* Contents of Entry Lo0 */
127    Addr PFN0; // Physical Frame Number - Even
128    bool D0;   // Even entry Dirty Bit
129    bool V0;   // Even entry Valid Bit
130    uint8_t C0; // Cache Coherency Bits - Even
131
132    /* Contents of Entry Lo1 */
133    Addr PFN1; // Physical Frame Number - Odd
134    bool D1;   // Odd entry Dirty Bit
135    bool V1;   // Odd entry Valid Bit
136    uint8_t C1; // Cache Coherency Bits (3 bits)
137
138    // The next few variables are put in as optimizations to reduce TLB
139    // lookup overheads. For a given Mask, what is the address shift amount
140    // and what is the OffsetMask
141    int AddrShiftAmount;
142    int OffsetMask;
143
144    bool
145    Valid()
146    {
147        return (V0 | V1);
148    };
149
150    void serialize(std::ostream &os);
151
152    void unserialize(Checkpoint *cp, const std::string &section);
153};
154
155} // PowerISA namespace
156
157#endif // __ARCH_POWER_PAGETABLE_H__
158
159