isa_traits.hh revision 8542:7230ff0738e3 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Timothy M. Jones
31 *          Gabe Black
32 *          Stephen Hines
33 */
34
35#ifndef __ARCH_POWER_ISA_TRAITS_HH__
36#define __ARCH_POWER_ISA_TRAITS_HH__
37
38#include "arch/power/types.hh"
39#include "base/types.hh"
40#include "cpu/static_inst_fwd.hh"
41
42namespace BigEndianGuest {}
43
44namespace PowerISA
45{
46
47using namespace BigEndianGuest;
48
49StaticInstPtr decodeInst(ExtMachInst);
50
51// POWER DOES NOT have a delay slot
52#define ISA_HAS_DELAY_SLOT 0
53
54const Addr PageShift = 12;
55const Addr PageBytes = ULL(1) << PageShift;
56const Addr Page_Mask = ~(PageBytes - 1);
57const Addr PageOffset = PageBytes - 1;
58
59const Addr PteShift = 3;
60const Addr NPtePageShift = PageShift - PteShift;
61const Addr NPtePage = ULL(1) << NPtePageShift;
62const Addr PteMask = NPtePage - 1;
63
64const int LogVMPageSize = 12;  // 4K bytes
65const int VMPageSize = (1 << LogVMPageSize);
66
67const int MachineBytes = 4;
68
69// This is ori 0, 0, 0
70const ExtMachInst NoopMachInst = 0x60000000;
71
72// Memory accesses can be unaligned
73const bool HasUnalignedMemAcc = true;
74
75} // namespace PowerISA
76
77#endif // __ARCH_POWER_ISA_TRAITS_HH__
78